[PATCH 5/5] aarch64: Add rsr128 and wsr128 ACLE tests

[Victor Do Nascimento]

Extend existing unit tests for the ACLE system register manipulation
functions to include 128-bit tests.

gcc/testsuite/ChangeLog:

        * gcc/testsuite/gcc.target/aarch64/acle/rwsr.c (get_rsr128): New.
        (set_wsr128): Likewise.
---
 gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 30 +++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c 
b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
index 3af4b960306..e7725022316 100644
--- a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
+++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c
@@ -1,11 +1,15 @@
 /* Test the __arm_[r,w]sr ACLE intrinsics family.  */
 /* Check that function variants for different data types handle types 
correctly.  */
 /* { dg-do compile } */
-/* { dg-options "-O1 -march=armv8.4-a" } */
+/* { dg-options "-O1 -march=armv9.4-a+d128" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <arm_acle.h>
 
+#ifndef __ARM_FEATURE_SYSREG128
+#error "__ARM_FEATURE_SYSREG128 feature macro not defined."
+#endif
+
 /*
 ** get_rsr:
 ** ...
@@ -66,6 +70,17 @@ get_rsrf64 ()
   return __arm_rsrf64("trcseqstr");
 }
 
+/*
+** get_rsr128:
+**     mrrs    x0, x1, s3_0_c7_c4_0
+** ...
+*/
+__uint128_t
+get_rsr128 ()
+{
+  __arm_rsr128("par_el1");
+}
+
 /*
 ** set_wsr32:
 ** ...
@@ -129,6 +144,18 @@ set_wsrf64(double a)
   __arm_wsrf64("trcseqstr", a);
 }
 
+/*
+** set_wsr128:
+** ...
+**     msrr    s3_0_c7_c4_0, x0, x1
+** ...
+*/
+void
+set_wsr128 (__uint128_t c)
+{
+  __arm_wsr128 ("par_el1", c);
+}
+
 /*
 ** set_custom:
 ** ...
@@ -142,3 +169,4 @@ void set_custom()
   __uint64_t b = __arm_rsr64("S1_2_C3_C4_5");
   __arm_wsr64("S1_2_C3_C4_5", b);
 }
+
-- 
2.41.0