Victor Do Nascimento <victor.donascime...@arm.com> writes:
> Given the introduction of system registers associated with the Guarded
> Control Stack extension to Armv9.4-a in Binutils and their reliance on
> the `+gcs' modifier, we implement the necessary changes in GCC to
> allow for them to be recognized by the compiler.
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-option-extensions.def (gcs): New.
> * config/aarch64/aarch64.h (AARCH64_ISA_GCS): New.
> (TARGET_THE): Likewise.
> * doc/invoke.texi (AArch64 Options): Describe GCS.
OK, thanks.
Richard
> ---
> gcc/config/aarch64/aarch64-option-extensions.def | 2 ++
> gcc/config/aarch64/aarch64.h | 6 ++++++
> gcc/doc/invoke.texi | 2 ++
> 3 files changed, 10 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
> b/gcc/config/aarch64/aarch64-option-extensions.def
> index da31f7c32d1..e72c039b612 100644
> --- a/gcc/config/aarch64/aarch64-option-extensions.def
> +++ b/gcc/config/aarch64/aarch64-option-extensions.def
> @@ -155,4 +155,6 @@ AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128")
>
> AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
>
> +AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
> +
> #undef AARCH64_OPT_EXTENSION
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index 1b3c800ec89..69ef54553d7 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -230,6 +230,7 @@ enum class aarch64_feature : unsigned char {
> #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC)
> #define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128)
> #define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE)
> +#define AARCH64_ISA_GCS (aarch64_isa_flags & AARCH64_FL_GCS)
>
> /* AARCH64_FL options necessary for system register implementation. */
>
> @@ -403,6 +404,11 @@ enum class aarch64_feature : unsigned char {
> enabled through +the. */
> #define TARGET_THE (AARCH64_ISA_THE)
>
> +/* Armv9.4-A Guarded Control Stack extension system registers are
> + enabled through +gcs. */
> +#define TARGET_GCS (AARCH64_ISA_GCS)
> +
> +
> /* Standard register usage. */
>
> /* 31 64-bit general purpose registers R0-R30:
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 88327ce9681..88ee1fdb524 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -21032,6 +21032,8 @@ Enable the Pointer Authentication Extension.
> Enable the Common Short Sequence Compression instructions.
> @item d128
> Enable support for 128-bit system register read/write instructions.
> +@item gcs
> +Enable support for Armv9.4-a Guarded Control Stack extension.
> @item the
> Enable support for Armv8.9-a/9.4-a translation hardening extension.
