On 2023-12-11 04:43 Jeff Law <jeffreya...@gmail.com> wrote: > > > >On 12/5/23 01:12, Fei Gao wrote: >> op=[ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT] >> >> Conditional op, if zero >> rd = (rc == 0) ? (rs1 op rs2) : rs1 >> --> >> czero.nez rd, rs2, rc >> op rd, rs1, rd >> >> Conditional op, if non-zero >> rd = (rc != 0) ? (rs1 op rs2) : rs1 >> --> >> czero.eqz rd, rs2, rc >> op rd, rs1, rd >> >> Co-authored-by: Xiao Zeng<zengx...@eswincomputing.com> >> >> gcc/ChangeLog: >> >> * ifcvt.cc (noce_cond_zero_binary_op_supported): add support for shift like >> op. >> (get_base_reg): add support for subreg to handle shift amount >>operand. >> (noce_bbs_ok_for_cond_zero_arith): to replace shift amount operand. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/riscv/zicond_ifcvt_opt.c: add TCs for shift like op. >So I removed the SUBREG handling code which makes this patch merely an >addition of the shift/rotate ops which trivally work just like PLUS, >MINUS, IOR, XOR (by conditionally zero-ing the shift count) tested on >x86 and pushed it to the trunk. > >As I noted before while I think handling SUBREGs is important, now is >not the time to be adding that support.
Thanks for your review. Got your point to defer support for SUBREGs. Shift-like pattern: (set (reg/v:DI 137 [ y ]) (ashift:DI (reg/v:DI 137 [ y ]) (subreg:QI (reg/v:DI 138 [ z ]) 0))) No Zicond instructions are generated with the SUBREG handling code removed. So I noticed your changes in testcases regarding the number of czero instruction number scanned. Then this looks like a NFC patch. BR, Fei > >Thanks! > >jeff
