v2 -> v3: * Removed duplicate ftype. This patch series presents the comprehensive implementation of the SIMD extension for CORE-V.
Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett <mary.benn...@embecosm.com> Nandni Jamnadas <nandni.jamna...@embecosm.com> Pietra Ferreira <pietra.ferre...@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackm...@embecosm.com> Simon Cook <simon.c...@embecosm.com> Jeremy Bennett <jeremy.benn...@embecosm.com> Helene Chelin <helene.che...@embecosm.com> RISC-V: Add support for XCVsimd extension in CV32E40P RISC-V: Fix XCValu test gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 8 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + 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