It's stage 4, so I think it would be great to not disturb code base too much, and adding intrinsic without adding VLS modes should be better way to go, and here is not really something serious coding style issue, just few minor indentation issue, so I gonna run regression to make not break anything else and then commit to trunk :)
- [PATCH v2 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett
- [PATCH v2 2/2] RISC-V: Fix XCValu test Mary Bennett
- [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Mary Bennett
- [PATCH v3 2/2] RISC-V: Fix XCValu test Mary Bennett
- Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD ex... Kito Cheng
