This patch implements the optabs reduc_and_scal_<mode>, reduc_ior_scal_<mode>, and reduc_xor_scal_<mode> for Advanced SIMD integers for TARGET_SVE in order to use the SVE instructions ANDV, ORV, and EORV for fixed-width bitwise reductions. For example, the test case
int32_t foo (int32_t *a)
{
int32_t b = -1;
for (int i = 0; i < 4; ++i)
b &= a[i];
return b;
}
was previously compiled to
(-O2 -ftree-vectorize --param aarch64-autovec-preference=asimd-only):
foo:
ldp w2, w1, [x0]
ldp w3, w0, [x0, 8]
and w1, w1, w3
and w0, w0, w2
and w0, w1, w0
ret
With patch, it is compiled to:
foo:
ldr q31, [x0]
ptrue p7.b, all
andv s31, p7, z31.s
fmov w0, s3
ret
Test cases were added to check the produced assembly for use of SVE
instructions.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Jennifer Schmitz <jschm...@nvidia.com>
gcc/
PR target/113816
* config/aarch64/aarch64-sve.md (reduc_<optab>_scal_<mode>): For
logical reductions, match operand 1 with VQ_I.
(*aarch64_pred_reduc_<optab>_<mode>): Likewise.
* config/aarch64/iterators.md (SVE_INT_REDUCTION_LOGICAL): New iterator
for logical reduction expressions.
gcc/testsuite
PR target/113816
* gcc.target/aarch64/sve/logical_reduc.c: New test.
0001-PR113816-AArch64-Use-SVE-bit-op-reduction-for-vector.patch
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