On 11/13/24 3:04 AM, Jin Ma wrote:
Since XTheadvector does not support vsetivli, vl needs to be put into
registers during the expand phase.
PR 116593
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc
(function_expander::add_input_operand):
Put const to GPR for vl
* config/riscv/thead-vector.md (@th_pred_vl_mov<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr116593.c: New test.
+
+ /* Since the parameter vl of XTheadVector does not support
+ immediate numbers, we need to put it in the register
+ in advance. */
+ if (TARGET_XTHEADVECTOR
+ && CONST_INT_P (x)
+ && base->apply_vl_p ()
+ && argno == (unsigned) (call_expr_nargs (exp) - 1)
+ && !rtx_equal_p (x, const0_rtx))
Last condition is better written as
x != CONST0_RTX (GET_MODE (x))
+ {
+ rtx tmp = gen_reg_rtx (Pmode);
+ /* Use UNSPEC to avoid being optimized before vsetvl pass. */
+ emit_insn (gen_th_pred_vl_mov (Pmode, tmp, x));
Pmode seems wrong. word_mode would likely be better. That would mean
some adjustment to your new insn.
Additionally, I'd like to understand better why you can't just
tmp = force_reg (word_mode, x);
Can you explain in more detail what you're trying to avoid? ie, RTL
before/after the problematical optimization? It feels like you're
papering over a bigger problem using the UNSPEC.
Can you also resubmit with the RSIC-V in the subject line fixed to
RISC-V that way the pre-commit tester will pick it up.
Thanks,
Jeff
