HI, Jeff
I am very sorry that I took so long to reply because I was ill and hospitalized.
> > +
> > + /* Since the parameter vl of XTheadVector does not support
> > + immediate numbers, we need to put it in the register
> > + in advance. */
> > + if (TARGET_XTHEADVECTOR
> > + && CONST_INT_P (x)
> > + && base->apply_vl_p ()
> > + && argno == (unsigned) (call_expr_nargs (exp) - 1)
> > + && !rtx_equal_p (x, const0_rtx))
> Last condition is better written as
> x != CONST0_RTX (GET_MODE (x))
Ok
>
> > + {
> > + rtx tmp = gen_reg_rtx (Pmode);
> > + /* Use UNSPEC to avoid being optimized before vsetvl pass. */
> > + emit_insn (gen_th_pred_vl_mov (Pmode, tmp, x));
> Pmode seems wrong. word_mode would likely be better. That would mean
> some adjustment to your new insn.
>
> Additionally, I'd like to understand better why you can't just
> tmp = force_reg (word_mode, x);
>
> Can you explain in more detail what you're trying to avoid? ie, RTL
> before/after the problematical optimization? It feels like you're
> papering over a bigger problem using the UNSPEC.
In fact, we inserted the vsetvl instruction in the "vsetvl" pass. Before it,
there will be many opportunities to eliminate the mov instruction we need,
such as "combine" pass or "reload" pass(curr_insn_transform), which will
eventually lead to vl in the vector pattern being an immediate instead of
a register. This will lead to only "vsetivli" being generated in the "vsetvl"
pass, which is obviously inconsistent with expectations. So we need a special
mov with UNSPEC to avoid it being optimized before the "vsetvl" pass.
>
> Can you also resubmit with the RSIC-V in the subject line fixed to
> RISC-V that way the pre-commit tester will pick it up.
Ok
> Thanks,
>
> Jeff
BR
Jin
