Leverage the centralized riscv-ext.def definitions to auto-generate
the target option parsing and associated internal flags, replacing
manual listings in riscv.opt; `riscv_ext_flag_table` part will remove in
later patch.
gcc/ChangeLog:
* config/riscv/gen-riscv-ext-opt.cc: New.
* config/riscv/riscv.opt: Drop manual entries for target
options, and include riscv-ext.opt.
* config/riscv/riscv-ext.opt: New.
* config/riscv/riscv-ext.opt.urls: New.
* config.gcc: Add riscv-ext.opt to the list of target options files.
* config/riscv/riscv-common.cc (riscv_ext_flag_table): Adjsut target
option variable entry.
(riscv_set_arch_by_subset_list): Adjust target option variable.
* config/riscv/riscv-c.cc (riscv_ext_flag_table): Adjust target
option variable entry.
* config/riscv/riscv-vector-builtins.cc (pragma_intrinsic_flags):
Adjust variable name.
(riscv_pragma_intrinsic_flags_pollute): Adjust variable name.
(riscv_pragma_intrinsic_flags_restore): Ditto.
* config/riscv/t-riscv: Add the rule for generating
riscv-ext.opt.
---
gcc/common/config/riscv/riscv-common.cc | 102 +++---
gcc/config.gcc | 1 +
gcc/config/riscv/gen-riscv-ext-opt.cc | 105 ++++++
gcc/config/riscv/riscv-c.cc | 8 +-
gcc/config/riscv/riscv-ext.opt | 400 ++++++++++++++++++++++
gcc/config/riscv/riscv-ext.opt.urls | 0
gcc/config/riscv/riscv-opts.h | 12 +-
gcc/config/riscv/riscv-vector-builtins.cc | 20 +-
gcc/config/riscv/riscv.opt | 313 +----------------
gcc/config/riscv/t-riscv | 13 +
10 files changed, 595 insertions(+), 379 deletions(-)
create mode 100644 gcc/config/riscv/gen-riscv-ext-opt.cc
create mode 100644 gcc/config/riscv/riscv-ext.opt
create mode 100644 gcc/config/riscv/riscv-ext.opt.urls
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index ca14eb96b253..b5a06a46e0e7 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1638,14 +1638,14 @@ struct riscv_ext_flag_table_t {
/* Mapping table between extension to internal flag. */
static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{
- RISCV_EXT_FLAG_ENTRY ("e", x_target_flags, MASK_RVE),
- RISCV_EXT_FLAG_ENTRY ("m", x_target_flags, MASK_MUL),
- RISCV_EXT_FLAG_ENTRY ("a", x_target_flags, MASK_ATOMIC),
- RISCV_EXT_FLAG_ENTRY ("f", x_target_flags, MASK_HARD_FLOAT),
- RISCV_EXT_FLAG_ENTRY ("d", x_target_flags, MASK_DOUBLE_FLOAT),
- RISCV_EXT_FLAG_ENTRY ("c", x_target_flags, MASK_RVC),
- RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_FULL_V),
- RISCV_EXT_FLAG_ENTRY ("v", x_target_flags, MASK_VECTOR),
+ RISCV_EXT_FLAG_ENTRY ("e", x_riscv_base_subext, MASK_RVE),
+ RISCV_EXT_FLAG_ENTRY ("m", x_riscv_base_subext, MASK_MUL),
+ RISCV_EXT_FLAG_ENTRY ("a", x_riscv_base_subext, MASK_ATOMIC),
+ RISCV_EXT_FLAG_ENTRY ("f", x_riscv_base_subext, MASK_HARD_FLOAT),
+ RISCV_EXT_FLAG_ENTRY ("d", x_riscv_base_subext, MASK_DOUBLE_FLOAT),
+ RISCV_EXT_FLAG_ENTRY ("c", x_riscv_base_subext, MASK_RVC),
+ RISCV_EXT_FLAG_ENTRY ("v", x_riscv_isa_flags, MASK_FULL_V),
+ RISCV_EXT_FLAG_ENTRY ("v", x_riscv_isa_flags, MASK_VECTOR),
RISCV_EXT_FLAG_ENTRY ("zicsr", x_riscv_zi_subext, MASK_ZICSR),
RISCV_EXT_FLAG_ENTRY ("zifencei", x_riscv_zi_subext, MASK_ZIFENCEI),
@@ -1688,22 +1688,22 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
RISCV_EXT_FLAG_ENTRY ("zicclsm", x_riscv_zi_subext, MASK_ZICCLSM),
RISCV_EXT_FLAG_ENTRY ("ziccrse", x_riscv_zi_subext, MASK_ZICCRSE),
- RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zicmo_subext, MASK_ZICBOZ),
- RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zicmo_subext, MASK_ZICBOM),
- RISCV_EXT_FLAG_ENTRY ("zicbop", x_riscv_zicmo_subext, MASK_ZICBOP),
- RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zicmo_subext, MASK_ZIC64B),
+ RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zi_subext, MASK_ZICBOZ),
+ RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zi_subext, MASK_ZICBOM),
+ RISCV_EXT_FLAG_ENTRY ("zicbop", x_riscv_zi_subext, MASK_ZICBOP),
+ RISCV_EXT_FLAG_ENTRY ("zic64b", x_riscv_zi_subext, MASK_ZIC64B),
RISCV_EXT_FLAG_ENTRY ("zicfiss", x_riscv_zi_subext, MASK_ZICFISS),
RISCV_EXT_FLAG_ENTRY ("zicfilp", x_riscv_zi_subext, MASK_ZICFILP),
- RISCV_EXT_FLAG_ENTRY ("zimop", x_riscv_mop_subext, MASK_ZIMOP),
- RISCV_EXT_FLAG_ENTRY ("zcmop", x_riscv_mop_subext, MASK_ZCMOP),
+ RISCV_EXT_FLAG_ENTRY ("zimop", x_riscv_zi_subext, MASK_ZIMOP),
+ RISCV_EXT_FLAG_ENTRY ("zcmop", x_riscv_zc_subext, MASK_ZCMOP),
- RISCV_EXT_FLAG_ENTRY ("zve32x", x_target_flags, MASK_VECTOR),
- RISCV_EXT_FLAG_ENTRY ("zve32f", x_target_flags, MASK_VECTOR),
- RISCV_EXT_FLAG_ENTRY ("zve64x", x_target_flags, MASK_VECTOR),
- RISCV_EXT_FLAG_ENTRY ("zve64f", x_target_flags, MASK_VECTOR),
- RISCV_EXT_FLAG_ENTRY ("zve64d", x_target_flags, MASK_VECTOR),
+ RISCV_EXT_FLAG_ENTRY ("zve32x", x_riscv_isa_flags, MASK_VECTOR),
+ RISCV_EXT_FLAG_ENTRY ("zve32f", x_riscv_isa_flags, MASK_VECTOR),
+ RISCV_EXT_FLAG_ENTRY ("zve64x", x_riscv_isa_flags, MASK_VECTOR),
+ RISCV_EXT_FLAG_ENTRY ("zve64f", x_riscv_isa_flags, MASK_VECTOR),
+ RISCV_EXT_FLAG_ENTRY ("zve64d", x_riscv_isa_flags, MASK_VECTOR),
/* We don't need to put complete ELEN/ELEN_FP info here, due to the
implication relation of vector extension.
@@ -1737,28 +1737,28 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
RISCV_EXT_FLAG_ENTRY ("zvksg", x_riscv_zvk_subext, MASK_ZVKSG),
RISCV_EXT_FLAG_ENTRY ("zvkt", x_riscv_zvk_subext, MASK_ZVKT),
- RISCV_EXT_FLAG_ENTRY ("zvl32b", x_riscv_zvl_flags, MASK_ZVL32B),
- RISCV_EXT_FLAG_ENTRY ("zvl64b", x_riscv_zvl_flags, MASK_ZVL64B),
- RISCV_EXT_FLAG_ENTRY ("zvl128b", x_riscv_zvl_flags, MASK_ZVL128B),
- RISCV_EXT_FLAG_ENTRY ("zvl256b", x_riscv_zvl_flags, MASK_ZVL256B),
- RISCV_EXT_FLAG_ENTRY ("zvl512b", x_riscv_zvl_flags, MASK_ZVL512B),
- RISCV_EXT_FLAG_ENTRY ("zvl1024b", x_riscv_zvl_flags, MASK_ZVL1024B),
- RISCV_EXT_FLAG_ENTRY ("zvl2048b", x_riscv_zvl_flags, MASK_ZVL2048B),
- RISCV_EXT_FLAG_ENTRY ("zvl4096b", x_riscv_zvl_flags, MASK_ZVL4096B),
- RISCV_EXT_FLAG_ENTRY ("zvl8192b", x_riscv_zvl_flags, MASK_ZVL8192B),
- RISCV_EXT_FLAG_ENTRY ("zvl16384b", x_riscv_zvl_flags, MASK_ZVL16384B),
- RISCV_EXT_FLAG_ENTRY ("zvl32768b", x_riscv_zvl_flags, MASK_ZVL32768B),
- RISCV_EXT_FLAG_ENTRY ("zvl65536b", x_riscv_zvl_flags, MASK_ZVL65536B),
+ RISCV_EXT_FLAG_ENTRY ("zvl32b", x_riscv_zvl_subext, MASK_ZVL32B),
+ RISCV_EXT_FLAG_ENTRY ("zvl64b", x_riscv_zvl_subext, MASK_ZVL64B),
+ RISCV_EXT_FLAG_ENTRY ("zvl128b", x_riscv_zvl_subext, MASK_ZVL128B),
+ RISCV_EXT_FLAG_ENTRY ("zvl256b", x_riscv_zvl_subext, MASK_ZVL256B),
+ RISCV_EXT_FLAG_ENTRY ("zvl512b", x_riscv_zvl_subext, MASK_ZVL512B),
+ RISCV_EXT_FLAG_ENTRY ("zvl1024b", x_riscv_zvl_subext, MASK_ZVL1024B),
+ RISCV_EXT_FLAG_ENTRY ("zvl2048b", x_riscv_zvl_subext, MASK_ZVL2048B),
+ RISCV_EXT_FLAG_ENTRY ("zvl4096b", x_riscv_zvl_subext, MASK_ZVL4096B),
+ RISCV_EXT_FLAG_ENTRY ("zvl8192b", x_riscv_zvl_subext, MASK_ZVL8192B),
+ RISCV_EXT_FLAG_ENTRY ("zvl16384b", x_riscv_zvl_subext, MASK_ZVL16384B),
+ RISCV_EXT_FLAG_ENTRY ("zvl32768b", x_riscv_zvl_subext, MASK_ZVL32768B),
+ RISCV_EXT_FLAG_ENTRY ("zvl65536b", x_riscv_zvl_subext, MASK_ZVL65536B),
RISCV_EXT_FLAG_ENTRY ("zfbfmin", x_riscv_zf_subext, MASK_ZFBFMIN),
RISCV_EXT_FLAG_ENTRY ("zfhmin", x_riscv_zf_subext, MASK_ZFHMIN),
RISCV_EXT_FLAG_ENTRY ("zfh", x_riscv_zf_subext, MASK_ZFH),
- RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_zf_subext, MASK_ZVFBFMIN),
- RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_zf_subext, MASK_ZVFBFWMA),
- RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_zf_subext, MASK_ZVFHMIN),
- RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_zf_subext, MASK_ZVFH),
+ RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_zvf_subext, MASK_ZVFBFMIN),
+ RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_zvf_subext, MASK_ZVFBFWMA),
+ RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_zvf_subext, MASK_ZVFHMIN),
+ RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_zvf_subext, MASK_ZVFH),
- RISCV_EXT_FLAG_ENTRY ("zfa", x_riscv_zfa_subext, MASK_ZFA),
+ RISCV_EXT_FLAG_ENTRY ("zfa", x_riscv_zf_subext, MASK_ZFA),
RISCV_EXT_FLAG_ENTRY ("zmmul", x_riscv_zm_subext, MASK_ZMMUL),
@@ -1777,7 +1777,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC),
- RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO),
+ RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_zt_subext, MASK_ZTSO),
RISCV_EXT_FLAG_ENTRY ("xcvmac", x_riscv_xcv_subext, MASK_XCVMAC),
RISCV_EXT_FLAG_ENTRY ("xcvalu", x_riscv_xcv_subext, MASK_XCVALU),
@@ -1803,21 +1803,21 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_FP_32),
RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_FP_64),
RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_FP_16),
- RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL32B),
- RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL64B),
- RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_flags, MASK_ZVL128B),
- RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zf_subext, MASK_ZVFHMIN),
- RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zf_subext, MASK_ZVFH),
- RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_target_flags, MASK_FULL_V),
- RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_target_flags, MASK_VECTOR),
+ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL32B),
+ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL64B),
+ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvl_subext, MASK_ZVL128B),
+ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvf_subext, MASK_ZVFHMIN),
+ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_zvf_subext, MASK_ZVFH),
+ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_FULL_V),
+ RISCV_EXT_FLAG_ENTRY ("xtheadvector", x_riscv_isa_flags, MASK_VECTOR),
RISCV_EXT_FLAG_ENTRY ("xventanacondops", x_riscv_xventana_subext,
MASK_XVENTANACONDOPS),
- RISCV_EXT_FLAG_ENTRY ("xsfvcp", x_riscv_sifive_subext, MASK_XSFVCP),
- RISCV_EXT_FLAG_ENTRY ("xsfcease", x_riscv_sifive_subext, MASK_XSFCEASE),
- RISCV_EXT_FLAG_ENTRY ("xsfvqmaccqoq", x_riscv_sifive_subext,
MASK_XSFVQMACCQOQ),
- RISCV_EXT_FLAG_ENTRY ("xsfvqmaccdod", x_riscv_sifive_subext,
MASK_XSFVQMACCDOD),
- RISCV_EXT_FLAG_ENTRY ("xsfvfnrclipxfqf", x_riscv_sifive_subext,
MASK_XSFVFNRCLIPXFQF),
+ RISCV_EXT_FLAG_ENTRY ("xsfvcp", x_riscv_xsf_subext, MASK_XSFVCP),
+ RISCV_EXT_FLAG_ENTRY ("xsfcease", x_riscv_xsf_subext, MASK_XSFCEASE),
+ RISCV_EXT_FLAG_ENTRY ("xsfvqmaccqoq", x_riscv_xsf_subext,
MASK_XSFVQMACCQOQ),
+ RISCV_EXT_FLAG_ENTRY ("xsfvqmaccdod", x_riscv_xsf_subext,
MASK_XSFVQMACCDOD),
+ RISCV_EXT_FLAG_ENTRY ("xsfvfnrclipxfqf", x_riscv_xsf_subext,
MASK_XSFVFNRCLIPXFQF),
{NULL, NULL, NULL, 0}
};
@@ -1855,9 +1855,9 @@ riscv_set_arch_by_subset_list (riscv_subset_list
*subset_list,
opts->*arch_ext_flag_tab->var_ref &= ~arch_ext_flag_tab->mask;
if (subset_list->xlen () == 32)
- opts->x_target_flags &= ~MASK_64BIT;
+ opts->x_riscv_isa_flags &= ~MASK_64BIT;
else if (subset_list->xlen () == 64)
- opts->x_target_flags |= MASK_64BIT;
+ opts->x_riscv_isa_flags |= MASK_64BIT;
for (arch_ext_flag_tab = &riscv_ext_flag_table[0];
arch_ext_flag_tab->ext;
diff --git a/gcc/config.gcc b/gcc/config.gcc
index afbf82fd2b8f..fee51469993b 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -558,6 +558,7 @@ riscv*)
extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h
riscv_th_vector.h sifive_vector.h"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.cc"
target_gtfiles="$target_gtfiles
\$(srcdir)/config/riscv/riscv-vector-builtins.h"
+ extra_options="${extra_options} riscv/riscv-ext.opt"
;;
rs6000*-*-*)
extra_options="${extra_options} g.opt fused-madd.opt
rs6000/rs6000-tables.opt"
diff --git a/gcc/config/riscv/gen-riscv-ext-opt.cc
b/gcc/config/riscv/gen-riscv-ext-opt.cc
new file mode 100644
index 000000000000..17b8f5bb1c0e
--- /dev/null
+++ b/gcc/config/riscv/gen-riscv-ext-opt.cc
@@ -0,0 +1,105 @@
+#include <vector>
+#include <string>
+#include <set>
+#include <stdio.h>
+#include "riscv-opts.h"
+
+struct version_t
+{
+ int major;
+ int minor;
+ version_t (int major, int minor,
+ enum riscv_isa_spec_class spec = ISA_SPEC_CLASS_NONE)
+ : major (major), minor (minor)
+ {}
+ bool operator<(const version_t &other) const
+ {
+ if (major != other.major)
+ return major < other.major;
+ return minor < other.minor;
+ }
+
+ bool operator== (const version_t &other) const
+ {
+ return major == other.major && minor == other.minor;
+ }
+};
+
+static void
+print_ext_doc_entry (const std::string &ext_name, const std::string &full_name,
+ const std::string &desc,
+ const std::vector<version_t> &supported_versions)
+{
+ // Implementation of the function to print the documentation entry
+ // for the extension.
+ std::set<version_t> unique_versions;
+ for (const auto &version : supported_versions)
+ unique_versions.insert (version);
+ printf ("@item %s\n", ext_name.c_str ());
+ printf ("@tab");
+ for (const auto &version : unique_versions)
+ {
+ printf (" %d.%d", version.major, version.minor);
+ }
+ printf ("\n");
+ printf ("@tab %s", full_name.c_str ());
+ if (desc.size ())
+ printf (", %s", desc.c_str ());
+ printf ("\n\n");
+}
+
+int
+main ()
+{
+ puts ("; Target options for the RISC-V port of the compiler");
+ puts (";");
+ puts ("; Copyright (C) 2025 Free Software Foundation, Inc.");
+ puts (";");
+ puts ("; This file is part of GCC.");
+ puts (";");
+ puts (
+ "; GCC is free software; you can redistribute it and/or modify it under");
+ puts (
+ "; the terms of the GNU General Public License as published by the Free");
+ puts (
+ "; Software Foundation; either version 3, or (at your option) any later");
+ puts ("; version.");
+ puts (";");
+ puts ("; GCC is distributed in the hope that it will be useful, but
WITHOUT");
+ puts ("; ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY");
+ puts ("; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public");
+ puts ("; License for more details.");
+ puts (";");
+ puts ("; You should have received a copy of the GNU General Public License");
+ puts ("; along with GCC; see the file COPYING3. If not see ");
+ puts ("; <http://www.gnu.org/licenses/>.");
+
+ puts ("; This file is generated automatically using");
+ puts ("; gcc/config/riscv/gen-riscv-ext-opt.cc from:");
+ puts ("; gcc/config/riscv/riscv-ext.def");
+ puts ("");
+ puts ("; Please *DO NOT* edit manually.");
+
+ std::set<std::string> all_vars;
+#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS,
\
+ SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \
+ BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \
+ all_vars.insert ("riscv_" #FLAG_GROUP "_subext");
+#include "riscv-ext.def"
+#undef DEFINE_RISCV_EXT
+
+ for (auto var : all_vars)
+ {
+ puts ("TargetVariable");
+ printf ("int %s\n\n", var.c_str ());
+ }
+
+#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS,
\
+ SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \
+ BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \
+ puts ("Mask(" #UPPERCAE_NAME ") Var(riscv_" #FLAG_GROUP "_subext)\n");
+#include "riscv-ext.def"
+#undef DEFINE_RISCV_EXT
+
+ return 0;
+}
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index ab6dc8389641..c86dcf791d64 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -39,7 +39,7 @@ struct pragma_intrinsic_flags
int intrinsic_target_flags;
int intrinsic_riscv_vector_elen_flags;
- int intrinsic_riscv_zvl_flags;
+ int intrinsic_riscv_zvl_subext;
int intrinsic_riscv_zvb_subext;
int intrinsic_riscv_zvk_subext;
};
@@ -49,14 +49,14 @@ riscv_pragma_intrinsic_flags_pollute (struct
pragma_intrinsic_flags *flags)
{
flags->intrinsic_target_flags = target_flags;
flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags;
- flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags;
+ flags->intrinsic_riscv_zvl_subext = riscv_zvl_subext;
flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext;
flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext;
target_flags = target_flags
| MASK_VECTOR;
- riscv_zvl_flags = riscv_zvl_flags
+ riscv_zvl_subext = riscv_zvl_subext
| MASK_ZVL32B
| MASK_ZVL64B
| MASK_ZVL128B
@@ -100,7 +100,7 @@ riscv_pragma_intrinsic_flags_restore (struct
pragma_intrinsic_flags *flags)
target_flags = flags->intrinsic_target_flags;
riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags;
- riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags;
+ riscv_zvl_subext = flags->intrinsic_riscv_zvl_subext;
riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext;
riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext;
}
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
new file mode 100644
index 000000000000..4efc0359b1d9
--- /dev/null
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -0,0 +1,400 @@
+; Target options for the RISC-V port of the compiler
+;
+; Copyright (C) 2025 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 3, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3. If not see
+; <http://www.gnu.org/licenses/>.
+; This file is generated automatically using
+; gcc/config/riscv/gen-riscv-ext-opt.cc from:
+; gcc/config/riscv/riscv-ext.def
+
+; Please *DO NOT* edit manually.
+TargetVariable
+int riscv_base_subext
+
+TargetVariable
+int riscv_sd_subext
+
+TargetVariable
+int riscv_sm_subext
+
+TargetVariable
+int riscv_ss_subext
+
+TargetVariable
+int riscv_su_subext
+
+TargetVariable
+int riscv_sv_subext
+
+TargetVariable
+int riscv_xcv_subext
+
+TargetVariable
+int riscv_xsf_subext
+
+TargetVariable
+int riscv_xthead_subext
+
+TargetVariable
+int riscv_xventana_subext
+
+TargetVariable
+int riscv_za_subext
+
+TargetVariable
+int riscv_zb_subext
+
+TargetVariable
+int riscv_zc_subext
+
+TargetVariable
+int riscv_zf_subext
+
+TargetVariable
+int riscv_zi_subext
+
+TargetVariable
+int riscv_zinx_subext
+
+TargetVariable
+int riscv_zk_subext
+
+TargetVariable
+int riscv_zm_subext
+
+TargetVariable
+int riscv_zt_subext
+
+TargetVariable
+int riscv_zvb_subext
+
+TargetVariable
+int riscv_zve_subext
+
+TargetVariable
+int riscv_zvf_subext
+
+TargetVariable
+int riscv_zvk_subext
+
+TargetVariable
+int riscv_zvl_subext
+
+Mask(RVE) Var(riscv_base_subext)
+
+Mask(RVI) Var(riscv_base_subext)
+
+Mask(MUL) Var(riscv_base_subext)
+
+Mask(ATOMIC) Var(riscv_base_subext)
+
+Mask(HARD_FLOAT) Var(riscv_base_subext)
+
+Mask(DOUBLE_FLOAT) Var(riscv_base_subext)
+
+Mask(RVC) Var(riscv_base_subext)
+
+Mask(RVB) Var(riscv_base_subext)
+
+Mask(RVV) Var(riscv_base_subext)
+
+Mask(RVH) Var(riscv_base_subext)
+
+Mask(ZIC64B) Var(riscv_zi_subext)
+
+Mask(ZICBOM) Var(riscv_zi_subext)
+
+Mask(ZICBOP) Var(riscv_zi_subext)
+
+Mask(ZICBOZ) Var(riscv_zi_subext)
+
+Mask(ZICCAMOA) Var(riscv_zi_subext)
+
+Mask(ZICCIF) Var(riscv_zi_subext)
+
+Mask(ZICCLSM) Var(riscv_zi_subext)
+
+Mask(ZICCRSE) Var(riscv_zi_subext)
+
+Mask(ZICFILP) Var(riscv_zi_subext)
+
+Mask(ZICFISS) Var(riscv_zi_subext)
+
+Mask(ZICNTR) Var(riscv_zi_subext)
+
+Mask(ZICOND) Var(riscv_zi_subext)
+
+Mask(ZICSR) Var(riscv_zi_subext)
+
+Mask(ZIFENCEI) Var(riscv_zi_subext)
+
+Mask(ZIHINTNTL) Var(riscv_zi_subext)
+
+Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
+
+Mask(ZIHPM) Var(riscv_zi_subext)
+
+Mask(ZIMOP) Var(riscv_zi_subext)
+
+Mask(ZMMUL) Var(riscv_zm_subext)
+
+Mask(ZA128RS) Var(riscv_za_subext)
+
+Mask(ZA64RS) Var(riscv_za_subext)
+
+Mask(ZAAMO) Var(riscv_za_subext)
+
+Mask(ZABHA) Var(riscv_za_subext)
+
+Mask(ZACAS) Var(riscv_za_subext)
+
+Mask(ZALRSC) Var(riscv_za_subext)
+
+Mask(ZAWRS) Var(riscv_za_subext)
+
+Mask(ZAMA16B) Var(riscv_za_subext)
+
+Mask(ZFA) Var(riscv_zf_subext)
+
+Mask(ZFBFMIN) Var(riscv_zf_subext)
+
+Mask(ZFH) Var(riscv_zf_subext)
+
+Mask(ZFHMIN) Var(riscv_zf_subext)
+
+Mask(ZFINX) Var(riscv_zinx_subext)
+
+Mask(ZDINX) Var(riscv_zinx_subext)
+
+Mask(ZCA) Var(riscv_zc_subext)
+
+Mask(ZCB) Var(riscv_zc_subext)
+
+Mask(ZCD) Var(riscv_zc_subext)
+
+Mask(ZCE) Var(riscv_zc_subext)
+
+Mask(ZCF) Var(riscv_zc_subext)
+
+Mask(ZCMOP) Var(riscv_zc_subext)
+
+Mask(ZCMP) Var(riscv_zc_subext)
+
+Mask(ZCMT) Var(riscv_zc_subext)
+
+Mask(ZBA) Var(riscv_zb_subext)
+
+Mask(ZBB) Var(riscv_zb_subext)
+
+Mask(ZBC) Var(riscv_zb_subext)
+
+Mask(ZBKB) Var(riscv_zb_subext)
+
+Mask(ZBKC) Var(riscv_zb_subext)
+
+Mask(ZBKX) Var(riscv_zb_subext)
+
+Mask(ZBS) Var(riscv_zb_subext)
+
+Mask(ZK) Var(riscv_zk_subext)
+
+Mask(ZKN) Var(riscv_zk_subext)
+
+Mask(ZKND) Var(riscv_zk_subext)
+
+Mask(ZKNE) Var(riscv_zk_subext)
+
+Mask(ZKNH) Var(riscv_zk_subext)
+
+Mask(ZKR) Var(riscv_zk_subext)
+
+Mask(ZKS) Var(riscv_zk_subext)
+
+Mask(ZKSED) Var(riscv_zk_subext)
+
+Mask(ZKSH) Var(riscv_zk_subext)
+
+Mask(ZKT) Var(riscv_zk_subext)
+
+Mask(ZTSO) Var(riscv_zt_subext)
+
+Mask(ZVBB) Var(riscv_zvb_subext)
+
+Mask(ZVBC) Var(riscv_zvb_subext)
+
+Mask(ZVE32F) Var(riscv_zve_subext)
+
+Mask(ZVE32X) Var(riscv_zve_subext)
+
+Mask(ZVE64D) Var(riscv_zve_subext)
+
+Mask(ZVE64F) Var(riscv_zve_subext)
+
+Mask(ZVE64X) Var(riscv_zve_subext)
+
+Mask(ZVFBFMIN) Var(riscv_zvf_subext)
+
+Mask(ZVFBFWMA) Var(riscv_zvf_subext)
+
+Mask(ZVFH) Var(riscv_zvf_subext)
+
+Mask(ZVFHMIN) Var(riscv_zvf_subext)
+
+Mask(ZVKB) Var(riscv_zvk_subext)
+
+Mask(ZVKG) Var(riscv_zvk_subext)
+
+Mask(ZVKN) Var(riscv_zvk_subext)
+
+Mask(ZVKNC) Var(riscv_zvk_subext)
+
+Mask(ZVKNED) Var(riscv_zvk_subext)
+
+Mask(ZVKNG) Var(riscv_zvk_subext)
+
+Mask(ZVKNHA) Var(riscv_zvk_subext)
+
+Mask(ZVKNHB) Var(riscv_zvk_subext)
+
+Mask(ZVKS) Var(riscv_zvk_subext)
+
+Mask(ZVKSC) Var(riscv_zvk_subext)
+
+Mask(ZVKSED) Var(riscv_zvk_subext)
+
+Mask(ZVKSG) Var(riscv_zvk_subext)
+
+Mask(ZVKSH) Var(riscv_zvk_subext)
+
+Mask(ZVKT) Var(riscv_zvk_subext)
+
+Mask(ZVL1024B) Var(riscv_zvl_subext)
+
+Mask(ZVL128B) Var(riscv_zvl_subext)
+
+Mask(ZVL16384B) Var(riscv_zvl_subext)
+
+Mask(ZVL2048B) Var(riscv_zvl_subext)
+
+Mask(ZVL256B) Var(riscv_zvl_subext)
+
+Mask(ZVL32768B) Var(riscv_zvl_subext)
+
+Mask(ZVL32B) Var(riscv_zvl_subext)
+
+Mask(ZVL4096B) Var(riscv_zvl_subext)
+
+Mask(ZVL512B) Var(riscv_zvl_subext)
+
+Mask(ZVL64B) Var(riscv_zvl_subext)
+
+Mask(ZVL65536B) Var(riscv_zvl_subext)
+
+Mask(ZVL8192B) Var(riscv_zvl_subext)
+
+Mask(ZHINX) Var(riscv_zinx_subext)
+
+Mask(ZHINXMIN) Var(riscv_zinx_subext)
+
+Mask(SDTRIG) Var(riscv_sd_subext)
+
+Mask(SMAIA) Var(riscv_sm_subext)
+
+Mask(SMEPMP) Var(riscv_sm_subext)
+
+Mask(SMMPM) Var(riscv_sm_subext)
+
+Mask(SMNPM) Var(riscv_sm_subext)
+
+Mask(SMSTATEEN) Var(riscv_sm_subext)
+
+Mask(SSAIA) Var(riscv_ss_subext)
+
+Mask(SSCOFPMF) Var(riscv_ss_subext)
+
+Mask(SSNPM) Var(riscv_ss_subext)
+
+Mask(SSPM) Var(riscv_ss_subext)
+
+Mask(SSSTATEEN) Var(riscv_ss_subext)
+
+Mask(SSTC) Var(riscv_ss_subext)
+
+Mask(SSSTRICT) Var(riscv_ss_subext)
+
+Mask(SUPM) Var(riscv_su_subext)
+
+Mask(SVINVAL) Var(riscv_sv_subext)
+
+Mask(SVNAPOT) Var(riscv_sv_subext)
+
+Mask(SVPBMT) Var(riscv_sv_subext)
+
+Mask(SVVPTC) Var(riscv_sv_subext)
+
+Mask(SVADU) Var(riscv_sv_subext)
+
+Mask(SVADE) Var(riscv_sv_subext)
+
+Mask(XCVALU) Var(riscv_xcv_subext)
+
+Mask(XCVBI) Var(riscv_xcv_subext)
+
+Mask(XCVELW) Var(riscv_xcv_subext)
+
+Mask(XCVMAC) Var(riscv_xcv_subext)
+
+Mask(XCVSIMD) Var(riscv_xcv_subext)
+
+Mask(XSFCEASE) Var(riscv_xsf_subext)
+
+Mask(XSFVCP) Var(riscv_xsf_subext)
+
+Mask(XSFVFNRCLIPXFQF) Var(riscv_xsf_subext)
+
+Mask(XSFVQMACCDOD) Var(riscv_xsf_subext)
+
+Mask(XSFVQMACCQOQ) Var(riscv_xsf_subext)
+
+Mask(XTHEADBA) Var(riscv_xthead_subext)
+
+Mask(XTHEADBB) Var(riscv_xthead_subext)
+
+Mask(XTHEADBS) Var(riscv_xthead_subext)
+
+Mask(XTHEADCMO) Var(riscv_xthead_subext)
+
+Mask(XTHEADCONDMOV) Var(riscv_xthead_subext)
+
+Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext)
+
+Mask(XTHEADFMV) Var(riscv_xthead_subext)
+
+Mask(XTHEADINT) Var(riscv_xthead_subext)
+
+Mask(XTHEADMAC) Var(riscv_xthead_subext)
+
+Mask(XTHEADMEMIDX) Var(riscv_xthead_subext)
+
+Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
+
+Mask(XTHEADSYNC) Var(riscv_xthead_subext)
+
+Mask(XTHEADVECTOR) Var(riscv_xthead_subext)
+
+Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
+
diff --git a/gcc/config/riscv/riscv-ext.opt.urls
b/gcc/config/riscv/riscv-ext.opt.urls
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 9766b89b2dff..fc3963c96bc5 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -136,16 +136,16 @@ enum rvv_vector_bits_enum {
/* Bit of riscv_zvl_flags will set continually, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to calculate the minimal VLEN. */
-#define TARGET_MIN_VLEN \
- ((riscv_zvl_flags == 0) \
- ? 0 \
- : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
+#define TARGET_MIN_VLEN
\
+ ((riscv_zvl_subext == 0)
\
+ ? 0
\
+ : 32 << (__builtin_popcount (riscv_zvl_subext) - 1))
/* Same as TARGET_MIN_VLEN, but take an OPTS as gcc_options. */
#define TARGET_MIN_VLEN_OPTS(opts)
\
- ((opts->x_riscv_zvl_flags == 0)
\
+ ((opts->x_riscv_zvl_subext == 0)
\
? 0
\
- : 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1))
+ : 32 << (__builtin_popcount (opts->x_riscv_zvl_subext) - 1))
/* The maximum LMUL according to user configuration. */
#define TARGET_MAX_LMUL
\
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index f3c706bfba90..f652a125dc35 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3842,26 +3842,26 @@ check_required_extensions (const function_instance
&instance)
required_extensions |= RVV_REQUIRE_RV64BIT;
}
- uint64_t riscv_isa_flags = 0;
+ uint64_t isa_flags = 0;
if (TARGET_VECTOR_ELEN_BF_16)
- riscv_isa_flags |= RVV_REQUIRE_ELEN_BF_16;
+ isa_flags |= RVV_REQUIRE_ELEN_BF_16;
if (TARGET_VECTOR_ELEN_FP_16)
- riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_16;
+ isa_flags |= RVV_REQUIRE_ELEN_FP_16;
if (TARGET_VECTOR_ELEN_FP_32)
- riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_32;
+ isa_flags |= RVV_REQUIRE_ELEN_FP_32;
if (TARGET_VECTOR_ELEN_FP_64)
- riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_64;
+ isa_flags |= RVV_REQUIRE_ELEN_FP_64;
if (TARGET_VECTOR_ELEN_64)
- riscv_isa_flags |= RVV_REQUIRE_ELEN_64;
+ isa_flags |= RVV_REQUIRE_ELEN_64;
if (TARGET_64BIT)
- riscv_isa_flags |= RVV_REQUIRE_RV64BIT;
+ isa_flags |= RVV_REQUIRE_RV64BIT;
if (TARGET_FULL_V)
- riscv_isa_flags |= RVV_REQUIRE_FULL_V;
+ isa_flags |= RVV_REQUIRE_FULL_V;
if (TARGET_MIN_VLEN > 32)
- riscv_isa_flags |= RVV_REQUIRE_MIN_VLEN_64;
+ isa_flags |= RVV_REQUIRE_MIN_VLEN_64;
- uint64_t missing_extensions = required_extensions & ~riscv_isa_flags;
+ uint64_t missing_extensions = required_extensions & ~isa_flags;
if (missing_extensions != 0)
return false;
return true;
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 80593ee139c1..527e09549a8a 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -168,23 +168,14 @@ momit-leaf-frame-pointer
Target Mask(OMIT_LEAF_FRAME_POINTER) Save
Omit the frame pointer in leaf functions.
-Mask(64BIT)
-
-Mask(MUL)
-
-Mask(ATOMIC)
-
-Mask(HARD_FLOAT)
-
-Mask(DOUBLE_FLOAT)
-
-Mask(RVC)
+TargetVariable
+int riscv_isa_flags
-Mask(RVE)
+Mask(64BIT) Var(riscv_isa_flags)
-Mask(VECTOR)
+Mask(VECTOR) Var(riscv_isa_flags)
-Mask(FULL_V)
+Mask(FULL_V) Var(riscv_isa_flags)
mriscv-attribute
Target Var(riscv_emit_attribute_p) Init(-1)
@@ -232,95 +223,6 @@ Use the given offset for addressing the stack-protector
guard.
TargetVariable
long riscv_stack_protector_guard_offset = 0
-TargetVariable
-int riscv_zi_subext
-
-Mask(ZICSR) Var(riscv_zi_subext)
-
-Mask(ZIFENCEI) Var(riscv_zi_subext)
-
-Mask(ZIHINTNTL) Var(riscv_zi_subext)
-
-Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
-
-Mask(ZICOND) Var(riscv_zi_subext)
-
-Mask(ZICCAMOA) Var(riscv_zi_subext)
-
-Mask(ZICCIF) Var(riscv_zi_subext)
-
-Mask(ZICCLSM) Var(riscv_zi_subext)
-
-Mask(ZICCRSE) Var(riscv_zi_subext)
-
-Mask(ZICFISS) Var(riscv_zi_subext)
-
-Mask(ZICFILP) Var(riscv_zi_subext)
-
-TargetVariable
-int riscv_za_subext
-
-Mask(ZAWRS) Var(riscv_za_subext)
-
-Mask(ZAAMO) Var(riscv_za_subext)
-
-Mask(ZALRSC) Var(riscv_za_subext)
-
-Mask(ZABHA) Var(riscv_za_subext)
-
-Mask(ZACAS) Var(riscv_za_subext)
-
-Mask(ZA64RS) Var(riscv_za_subext)
-
-Mask(ZA128RS) Var(riscv_za_subext)
-
-Mask(ZAMA16B) Var(riscv_za_subext)
-
-TargetVariable
-int riscv_zb_subext
-
-Mask(ZBA) Var(riscv_zb_subext)
-
-Mask(ZBB) Var(riscv_zb_subext)
-
-Mask(ZBC) Var(riscv_zb_subext)
-
-Mask(ZBS) Var(riscv_zb_subext)
-
-TargetVariable
-int riscv_zinx_subext
-
-Mask(ZFINX) Var(riscv_zinx_subext)
-
-Mask(ZDINX) Var(riscv_zinx_subext)
-
-Mask(ZHINX) Var(riscv_zinx_subext)
-
-Mask(ZHINXMIN) Var(riscv_zinx_subext)
-
-TargetVariable
-int riscv_zk_subext
-
-Mask(ZBKB) Var(riscv_zk_subext)
-
-Mask(ZBKC) Var(riscv_zk_subext)
-
-Mask(ZBKX) Var(riscv_zk_subext)
-
-Mask(ZKNE) Var(riscv_zk_subext)
-
-Mask(ZKND) Var(riscv_zk_subext)
-
-Mask(ZKNH) Var(riscv_zk_subext)
-
-Mask(ZKR) Var(riscv_zk_subext)
-
-Mask(ZKSED) Var(riscv_zk_subext)
-
-Mask(ZKSH) Var(riscv_zk_subext)
-
-Mask(ZKT) Var(riscv_zk_subext)
-
TargetVariable
int riscv_vector_elen_flags
@@ -336,211 +238,6 @@ Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags)
Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags)
-TargetVariable
-int riscv_zvl_flags
-
-Mask(ZVL32B) Var(riscv_zvl_flags)
-
-Mask(ZVL64B) Var(riscv_zvl_flags)
-
-Mask(ZVL128B) Var(riscv_zvl_flags)
-
-Mask(ZVL256B) Var(riscv_zvl_flags)
-
-Mask(ZVL512B) Var(riscv_zvl_flags)
-
-Mask(ZVL1024B) Var(riscv_zvl_flags)
-
-Mask(ZVL2048B) Var(riscv_zvl_flags)
-
-Mask(ZVL4096B) Var(riscv_zvl_flags)
-
-Mask(ZVL8192B) Var(riscv_zvl_flags)
-
-Mask(ZVL16384B) Var(riscv_zvl_flags)
-
-Mask(ZVL32768B) Var(riscv_zvl_flags)
-
-Mask(ZVL65536B) Var(riscv_zvl_flags)
-
-TargetVariable
-int riscv_zvb_subext
-
-Mask(ZVBB) Var(riscv_zvb_subext)
-
-Mask(ZVBC) Var(riscv_zvb_subext)
-
-Mask(ZVKB) Var(riscv_zvb_subext)
-
-TargetVariable
-int riscv_zvk_subext
-
-Mask(ZVKG) Var(riscv_zvk_subext)
-
-Mask(ZVKNED) Var(riscv_zvk_subext)
-
-Mask(ZVKNHA) Var(riscv_zvk_subext)
-
-Mask(ZVKNHB) Var(riscv_zvk_subext)
-
-Mask(ZVKSED) Var(riscv_zvk_subext)
-
-Mask(ZVKSH) Var(riscv_zvk_subext)
-
-Mask(ZVKN) Var(riscv_zvk_subext)
-
-Mask(ZVKNC) Var(riscv_zvk_subext)
-
-Mask(ZVKNG) Var(riscv_zvk_subext)
-
-Mask(ZVKS) Var(riscv_zvk_subext)
-
-Mask(ZVKSC) Var(riscv_zvk_subext)
-
-Mask(ZVKSG) Var(riscv_zvk_subext)
-
-Mask(ZVKT) Var(riscv_zvk_subext)
-
-TargetVariable
-int riscv_zicmo_subext
-
-Mask(ZICBOZ) Var(riscv_zicmo_subext)
-
-Mask(ZICBOM) Var(riscv_zicmo_subext)
-
-Mask(ZICBOP) Var(riscv_zicmo_subext)
-
-Mask(ZIC64B) Var(riscv_zicmo_subext)
-
-TargetVariable
-int riscv_mop_subext
-
-Mask(ZIMOP) Var(riscv_mop_subext)
-
-Mask(ZCMOP) Var(riscv_mop_subext)
-
-TargetVariable
-int riscv_zf_subext
-
-Mask(ZFBFMIN) Var(riscv_zf_subext)
-
-Mask(ZFHMIN) Var(riscv_zf_subext)
-
-Mask(ZFH) Var(riscv_zf_subext)
-
-Mask(ZVFBFMIN) Var(riscv_zf_subext)
-
-Mask(ZVFBFWMA) Var(riscv_zf_subext)
-
-Mask(ZVFHMIN) Var(riscv_zf_subext)
-
-Mask(ZVFH) Var(riscv_zf_subext)
-
-TargetVariable
-int riscv_zfa_subext
-
-Mask(ZFA) Var(riscv_zfa_subext)
-
-TargetVariable
-int riscv_zm_subext
-
-Mask(ZMMUL) Var(riscv_zm_subext)
-
-TargetVariable
-int riscv_zc_subext
-
-Mask(ZCA) Var(riscv_zc_subext)
-
-Mask(ZCB) Var(riscv_zc_subext)
-
-Mask(ZCE) Var(riscv_zc_subext)
-
-Mask(ZCF) Var(riscv_zc_subext)
-
-Mask(ZCD) Var(riscv_zc_subext)
-
-Mask(ZCMP) Var(riscv_zc_subext)
-
-Mask(ZCMT) Var(riscv_zc_subext)
-
-Mask(XCVBI) Var(riscv_xcv_subext)
-
-TargetVariable
-int riscv_sv_subext
-
-Mask(SVADE) Var(riscv_sv_subext)
-
-Mask(SVADU) Var(riscv_sv_subext)
-
-Mask(SVINVAL) Var(riscv_sv_subext)
-
-Mask(SVNAPOT) Var(riscv_sv_subext)
-
-Mask(SVVPTC) Var(riscv_sv_subext)
-
-TargetVariable
-int riscv_ztso_subext
-
-Mask(ZTSO) Var(riscv_ztso_subext)
-
-TargetVariable
-int riscv_xcv_subext
-
-Mask(XCVMAC) Var(riscv_xcv_subext)
-
-Mask(XCVALU) Var(riscv_xcv_subext)
-
-Mask(XCVELW) Var(riscv_xcv_subext)
-
-Mask(XCVSIMD) Var(riscv_xcv_subext)
-
-TargetVariable
-int riscv_xthead_subext
-
-Mask(XTHEADBA) Var(riscv_xthead_subext)
-
-Mask(XTHEADBB) Var(riscv_xthead_subext)
-
-Mask(XTHEADBS) Var(riscv_xthead_subext)
-
-Mask(XTHEADCMO) Var(riscv_xthead_subext)
-
-Mask(XTHEADCONDMOV) Var(riscv_xthead_subext)
-
-Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext)
-
-Mask(XTHEADFMV) Var(riscv_xthead_subext)
-
-Mask(XTHEADINT) Var(riscv_xthead_subext)
-
-Mask(XTHEADMAC) Var(riscv_xthead_subext)
-
-Mask(XTHEADMEMIDX) Var(riscv_xthead_subext)
-
-Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
-
-Mask(XTHEADSYNC) Var(riscv_xthead_subext)
-
-Mask(XTHEADVECTOR) Var(riscv_xthead_subext)
-
-TargetVariable
-int riscv_xventana_subext
-
-Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
-
-TargetVariable
-int riscv_sifive_subext
-
-Mask(XSFVCP) Var(riscv_sifive_subext)
-
-Mask(XSFCEASE) Var(riscv_sifive_subext)
-
-Mask(XSFVQMACCQOQ) Var(riscv_sifive_subext)
-
-Mask(XSFVQMACCDOD) Var(riscv_sifive_subext)
-
-Mask(XSFVFNRCLIPXFQF) Var(riscv_sifive_subext)
-
TargetVariable
int riscv_fmv_priority = 0
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 12e2b6e999a0..9a9fb1bc1b52 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -187,3 +187,16 @@ s-riscv-vector-type-indexer.gen.defs:
build/genrvv-type-indexer$(build_exeext)
$(STAMP) s-riscv-vector-type-indexer.gen.defs
genprog+=rvv-type-indexer
+
+$(srcdir)/config/riscv/riscv-ext.opt: $(srcdir)/config/riscv/riscv-ext.def
+
+$(srcdir)/config/riscv/riscv-ext.opt: s-riscv-ext.opt ; @true
+
+build/gen-riscv-ext-opt$(build_exeext):
$(srcdir)/config/riscv/gen-riscv-ext-opt.cc \
+ $(srcdir)/config/riscv/riscv-ext.def
+ $(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) $< -o $@
+
+s-riscv-ext.opt: build/gen-riscv-ext-opt$(build_exeext)
+ $(RUN_GEN) build/gen-riscv-ext-opt$(build_exeext) > tmp-riscv-ext.opt
+ $(SHELL) $(srcdir)/../move-if-change tmp-riscv-ext.opt
$(srcdir)/config/riscv/riscv-ext.opt
+ $(STAMP) s-riscv-ext.opt
--
2.34.1
