Automatically build the ISA extension reference table in invoke.texi from
the unified riscv-ext.def metadata, ensuring documentation stays in sync
with extension definitions and reducing manual maintenance.
gcc/ChangeLog:
* doc/invoke.texi: Replace hand‑written extension table with
`@include riscv-ext.texi` to pull in auto‑generated entries.
* doc/riscv-ext.texi: New generated definition file
containing formatted documentation entries for each extension.
* Makefile.in: Add riscv-ext.texi to the list of files to be
processed by the Texinfo generator.
* config/riscv/gen-riscv-ext-texi.cc: New.
* config/riscv/t-riscv: Add rule for generating riscv-ext.texi.
---
gcc/Makefile.in | 2 +-
gcc/config/riscv/gen-riscv-ext-texi.cc | 88 ++++
gcc/config/riscv/t-riscv | 34 +-
gcc/doc/invoke.texi | 495 +------------------
gcc/doc/riscv-ext.texi | 629 +++++++++++++++++++++++++
5 files changed, 751 insertions(+), 497 deletions(-)
create mode 100644 gcc/config/riscv/gen-riscv-ext-texi.cc
create mode 100644 gcc/doc/riscv-ext.texi
diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index 55b4cd7dbed3..0fa5d0c925af 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -3702,7 +3702,7 @@ TEXI_GCC_FILES = gcc.texi gcc-common.texi gcc-vers.texi
frontends.texi \
contribute.texi compat.texi funding.texi gnu.texi gpl_v3.texi \
fdl.texi contrib.texi cppenv.texi cppopts.texi avr-mmcu.texi \
implement-c.texi implement-cxx.texi gcov-tool.texi gcov-dump.texi \
- lto-dump.texi
+ lto-dump.texi riscv-ext.texi
# we explicitly use $(srcdir)/doc/tm.texi here to avoid confusion with
# the generated tm.texi; the latter might have a more recent timestamp,
diff --git a/gcc/config/riscv/gen-riscv-ext-texi.cc
b/gcc/config/riscv/gen-riscv-ext-texi.cc
new file mode 100644
index 000000000000..e15fdbf36f6e
--- /dev/null
+++ b/gcc/config/riscv/gen-riscv-ext-texi.cc
@@ -0,0 +1,88 @@
+#include <vector>
+#include <string>
+#include <set>
+#include <stdio.h>
+#include "riscv-opts.h"
+
+struct version_t
+{
+ int major;
+ int minor;
+ version_t (int major, int minor,
+ enum riscv_isa_spec_class spec = ISA_SPEC_CLASS_NONE)
+ : major (major), minor (minor)
+ {}
+ bool operator<(const version_t &other) const
+ {
+ if (major != other.major)
+ return major < other.major;
+ return minor < other.minor;
+ }
+
+ bool operator== (const version_t &other) const
+ {
+ return major == other.major && minor == other.minor;
+ }
+};
+
+static void
+print_ext_doc_entry (const std::string &ext_name, const std::string &full_name,
+ const std::string &desc,
+ const std::vector<version_t> &supported_versions)
+{
+ // Implementation of the function to print the documentation entry
+ // for the extension.
+ std::set<version_t> unique_versions;
+ for (const auto &version : supported_versions)
+ unique_versions.insert (version);
+ printf ("@item %s\n", ext_name.c_str ());
+ printf ("@tab");
+ for (const auto &version : unique_versions)
+ {
+ printf (" %d.%d", version.major, version.minor);
+ }
+ printf ("\n");
+ printf ("@tab %s", full_name.c_str ());
+ if (desc.size ())
+ printf (", %s", desc.c_str ());
+ printf ("\n\n");
+}
+
+int
+main ()
+{
+ puts ("@c Copyright (C) 2025 Free Software Foundation, Inc.");
+ puts ("@c This is part of the GCC manual.");
+ puts ("@c For copying conditions, see the file gcc/doc/include/fdl.texi.");
+ puts ("");
+ puts ("@c This file is generated automatically using");
+ puts ("@c gcc/config/riscv/gen-riscv-ext-texi.cc from:");
+ puts ("@c gcc/config/riscv/riscv-ext.def");
+ puts ("@c gcc/config/riscv/riscv-opts.h");
+ puts ("");
+ puts ("@c Please *DO NOT* edit manually.");
+ puts ("");
+ puts ("@multitable @columnfractions .10 .10 .80");
+ puts ("@headitem Extension Name @tab Supported Version @tab Description");
+ puts ("");
+
+ /* g extension is a very speical extension that no clear version... */
+ puts ("@item g");
+ puts ("@tab -");
+ puts (
+ "@tab General-purpose computing base extension, @samp{g} will expand to");
+ puts ("@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and");
+ puts ("@samp{zifencei}.");
+ puts ("");
+
+#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS,
\
+ SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \
+ BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \
+ print_ext_doc_entry (#NAME, FULL_NAME, DESC,
\
+ std::vector<version_t> SUPPORTED_VERSIONS);
+#include "riscv-ext.def"
+#undef DEFINE_RISCV_EXT
+
+ puts ("@end multitable");
+ return 0;
+}
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 9a9fb1bc1b52..e99d6689ba06 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -188,15 +188,45 @@ s-riscv-vector-type-indexer.gen.defs:
build/genrvv-type-indexer$(build_exeext)
genprog+=rvv-type-indexer
-$(srcdir)/config/riscv/riscv-ext.opt: $(srcdir)/config/riscv/riscv-ext.def
+RISCV_EXT_DEFS = \
+ $(srcdir)/config/riscv/riscv-ext.def \
+ $(srcdir)/config/riscv/riscv-ext-corev.def \
+ $(srcdir)/config/riscv/riscv-ext.def \
+ $(srcdir)/config/riscv/riscv-ext-sifive.def \
+ $(srcdir)/config/riscv/riscv-ext-thead.def \
+ $(srcdir)/config/riscv/riscv-ext-ventana.def
+
+$(srcdir)/config/riscv/riscv-ext.opt: $(RISCV_EXT_DEFS)
$(srcdir)/config/riscv/riscv-ext.opt: s-riscv-ext.opt ; @true
build/gen-riscv-ext-opt$(build_exeext):
$(srcdir)/config/riscv/gen-riscv-ext-opt.cc \
- $(srcdir)/config/riscv/riscv-ext.def
+ $(RISCV_EXT_DEFS)
$(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) $< -o $@
s-riscv-ext.opt: build/gen-riscv-ext-opt$(build_exeext)
$(RUN_GEN) build/gen-riscv-ext-opt$(build_exeext) > tmp-riscv-ext.opt
$(SHELL) $(srcdir)/../move-if-change tmp-riscv-ext.opt
$(srcdir)/config/riscv/riscv-ext.opt
$(STAMP) s-riscv-ext.opt
+
+build/gen-riscv-ext-texi$(build_exeext):
$(srcdir)/config/riscv/gen-riscv-ext-texi.cc \
+ $(RISCV_EXT_DEFS)
+ $(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) $< -o $@
+
+
+$(srcdir)/doc/riscv-ext.texi: $(RISCV_EXT_DEFS)
+$(srcdir)/doc/riscv-ext.texi: s-riscv-ext.texi ; @true
+
+# Generate the doc when generating option file.
+$(srcdir)/config/riscv/riscv-ext.opt: s-riscv-ext.texi ; @true
+
+s-riscv-ext.texi: build/gen-riscv-ext-texi$(build_exeext)
+ $(RUN_GEN) build/gen-riscv-ext-texi$(build_exeext) > tmp-riscv-ext.texi
+ $(SHELL) $(srcdir)/../move-if-change tmp-riscv-ext.texi
$(srcdir)/doc/riscv-ext.texi
+ $(STAMP) s-riscv-ext.texi
+
+# Run `riscv-regen' after you changed or added anything from riscv-ext*.def
+
+.PHONY: riscv-regen
+
+riscv-regen: s-riscv-ext.texi s-riscv-ext.opt
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b1964b3d3f57..84e355a28604 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31122,501 +31122,8 @@ syntax @samp{<major>p<minor>} or @samp{<major>},
(e.g.@: @samp{m2p1} or
@end table
Supported extension are listed below:
-@multitable @columnfractions .10 .10 .80
-@headitem Extension Name @tab Supported Version @tab Description
-@item i
-@tab 2.0, 2.1
-@tab Base integer extension.
-
-@item e
-@tab 2.0
-@tab Reduced base integer extension.
-
-@item g
-@tab -
-@tab General-purpose computing base extension, @samp{g} will expand to
-@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and
-@samp{zifencei}.
-
-@item m
-@tab 2.0
-@tab Integer multiplication and division extension.
-
-@item a
-@tab 2.0, 2.1
-@tab Atomic extension.
-
-@item f
-@tab 2.0, 2.2
-@tab Single-precision floating-point extension.
-
-@item d
-@tab 2.0, 2.2
-@tab Double-precision floating-point extension.
-
-@item c
-@tab 2.0
-@tab Compressed extension.
-
-@item h
-@tab 1.0
-@tab Hypervisor extension.
-
-@item v
-@tab 1.0
-@tab Vector extension.
-
-@item zicsr
-@tab 2.0
-@tab Control and status register access extension.
-
-@item zifencei
-@tab 2.0
-@tab Instruction-fetch fence extension.
-
-@item zicond
-@tab 1.0
-@tab Integer conditional operations extension.
-
-@item za64rs
-@tab 1.0
-@tab Reservation set size of 64 bytes.
-
-@item za128rs
-@tab 1.0
-@tab Reservation set size of 128 bytes.
-
-@item zawrs
-@tab 1.0
-@tab Wait-on-reservation-set extension.
-
-@item zba
-@tab 1.0
-@tab Address calculation extension.
-
-@item zbb
-@tab 1.0
-@tab Basic bit manipulation extension.
-
-@item zbc
-@tab 1.0
-@tab Carry-less multiplication extension.
-
-@item zbs
-@tab 1.0
-@tab Single-bit operation extension.
-
-@item zfinx
-@tab 1.0
-@tab Single-precision floating-point in integer registers extension.
-
-@item zdinx
-@tab 1.0
-@tab Double-precision floating-point in integer registers extension.
-
-@item zhinx
-@tab 1.0
-@tab Half-precision floating-point in integer registers extension.
-
-@item zhinxmin
-@tab 1.0
-@tab Minimal half-precision floating-point in integer registers extension.
-
-@item zbkb
-@tab 1.0
-@tab Cryptography bit-manipulation extension.
-
-@item zbkc
-@tab 1.0
-@tab Cryptography carry-less multiply extension.
-
-@item zbkx
-@tab 1.0
-@tab Cryptography crossbar permutation extension.
-
-@item zkne
-@tab 1.0
-@tab AES Encryption extension.
-
-@item zknd
-@tab 1.0
-@tab AES Decryption extension.
-
-@item zknh
-@tab 1.0
-@tab Hash function extension.
-
-@item zkr
-@tab 1.0
-@tab Entropy source extension.
-
-@item zksed
-@tab 1.0
-@tab SM4 block cipher extension.
-
-@item zksh
-@tab 1.0
-@tab SM3 hash function extension.
-
-@item zkt
-@tab 1.0
-@tab Data independent execution latency extension.
-
-@item zk
-@tab 1.0
-@tab Standard scalar cryptography extension.
-
-@item zkn
-@tab 1.0
-@tab NIST algorithm suite extension.
-
-@item zks
-@tab 1.0
-@tab ShangMi algorithm suite extension.
-@item zihintntl
-@tab 1.0
-@tab Non-temporal locality hints extension.
-
-@item zihintpause
-@tab 1.0
-@tab Pause hint extension.
-
-@item zicboz
-@tab 1.0
-@tab Cache-block zero extension.
-
-@item zicbom
-@tab 1.0
-@tab Cache-block management extension.
-
-@item zicbop
-@tab 1.0
-@tab Cache-block prefetch extension.
-
-@item zic64b
-@tab 1.0
-@tab Cache block size isf 64 bytes.
-
-@item ziccamoa
-@tab 1.0
-@tab Main memory supports all atomics in A.
-
-@item ziccif
-@tab 1.0
-@tab Main memory supports instruction fetch with atomicity requirement.
-
-@item zicclsm
-@tab 1.0
-@tab Main memory supports misaligned loads/stores.
-
-@item ziccrse
-@tab 1.0
-@tab Main memory supports forward progress on LR/SC sequences.
-
-@item zicntr
-@tab 2.0
-@tab Standard extension for base counters and timers.
-
-@item zihpm
-@tab 2.0
-@tab Standard extension for hardware performance counters.
-
-@item ztso
-@tab 1.0
-@tab Total store ordering extension.
-
-@item zve32x
-@tab 1.0
-@tab Vector extensions for embedded processors.
-
-@item zve32f
-@tab 1.0
-@tab Vector extensions for embedded processors.
-
-@item zve64x
-@tab 1.0
-@tab Vector extensions for embedded processors.
-
-@item zve64f
-@tab 1.0
-@tab Vector extensions for embedded processors.
-
-@item zve64d
-@tab 1.0
-@tab Vector extensions for embedded processors.
-
-@item zvl32b
-@tab 1.0
-@tab Minimum vector length standard extensions
-
-@item zvl64b
-@tab 1.0
-@tab Minimum vector length standard extensions
-
-@item zvl128b
-@tab 1.0
-@tab Minimum vector length standard extensions
-
-@item zvl256b
-@tab 1.0
-@tab Minimum vector length standard extensions
-
-@item zvl512b
-@tab 1.0
-@tab Minimum vector length standard extensions
-
-@item zvl1024b
-@tab 1.0
-@tab Minimum vector length standard extensions
-
-@item zvl2048b
-@tab 1.0
-@tab Minimum vector length standard extensions
-
-@item zvl4096b
-@tab 1.0
-@tab Minimum vector length standard extensions
-
-@item zvbb
-@tab 1.0
-@tab Vector basic bit-manipulation extension.
-
-@item zvbc
-@tab 1.0
-@tab Vector carryless multiplication extension.
-
-@item zvkb
-@tab 1.0
-@tab Vector cryptography bit-manipulation extension.
-
-@item zvkg
-@tab 1.0
-@tab Vector GCM/GMAC extension.
-
-@item zvkned
-@tab 1.0
-@tab Vector AES block cipher extension.
-
-@item zvknha
-@tab 1.0
-@tab Vector SHA-2 secure hash extension.
-
-@item zvknhb
-@tab 1.0
-@tab Vector SHA-2 secure hash extension.
-
-@item zvksed
-@tab 1.0
-@tab Vector SM4 Block Cipher extension.
-
-@item zvksh
-@tab 1.0
-@tab Vector SM3 Secure Hash extension.
-
-@item zvkn
-@tab 1.0
-@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to
-@samp{zvkned}, @samp{zvknhb}, @samp{zvkb} and @samp{zvkt}.
-
-@item zvknc
-@tab 1.0
-@tab Vector NIST Algorithm Suite with carryless multiply extension,
@samp{zvknc}
-will expand to @samp{zvkn} and @samp{zvbc}.
-
-@item zvkng
-@tab 1.0
-@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand
-to @samp{zvkn} and @samp{zvkg}.
-
-@item zvks
-@tab 1.0
-@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand
-to @samp{zvksed}, @samp{zvksh}, @samp{zvkb} and @samp{zvkt}.
-
-@item zvksc
-@tab 1.0
-@tab Vector ShangMi algorithm suite with carryless multiplication extension,
-@samp{zvksc} will expand to @samp{zvks} and @samp{zvbc}.
-
-@item zvksg
-@tab 1.0
-@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will
expand
-to @samp{zvks} and @samp{zvkg}.
-
-@item zvkt
-@tab 1.0
-@tab Vector data independent execution latency extension.
-
-@item zfh
-@tab 1.0
-@tab Half-precision floating-point extension.
-
-@item zfhmin
-@tab 1.0
-@tab Minimal half-precision floating-point extension.
-
-@item zvfh
-@tab 1.0
-@tab Vector half-precision floating-point extension.
-
-@item zvfhmin
-@tab 1.0
-@tab Vector minimal half-precision floating-point extension.
-
-@item zvfbfmin
-@tab 1.0
-@tab Vector BF16 converts extension.
-
-@item zfa
-@tab 1.0
-@tab Additional floating-point extension.
-
-@item zmmul
-@tab 1.0
-@tab Integer multiplication extension.
-
-@item zca
-@tab 1.0
-@tab Integer compressed instruction extension.
-
-@item zcf
-@tab 1.0
-@tab Compressed single-precision floating point loads and stores extension.
-
-@item zcd
-@tab 1.0
-@tab Compressed double-precision floating point loads and stores extension.
-
-@item zcb
-@tab 1.0
-@tab Simple compressed instruction extension.
-
-@item zce
-@tab 1.0
-@tab Compressed instruction extensions for embedded processors.
-
-@item zcmp
-@tab 1.0
-@tab Compressed push pop extension.
-
-@item zcmt
-@tab 1.0
-@tab Table jump instruction extension.
-
-@item smaia
-@tab 1.0
-@tab Advanced interrupt architecture extension.
-
-@item smepmp
-@tab 1.0
-@tab PMP Enhancements for memory access and execution prevention on Machine
mode.
-
-@item smstateen
-@tab 1.0
-@tab State enable extension.
-
-@item ssaia
-@tab 1.0
-@tab Advanced interrupt architecture extension for supervisor-mode.
-
-@item sscofpmf
-@tab 1.0
-@tab Count overflow & filtering extension.
-
-@item ssstateen
-@tab 1.0
-@tab State-enable extension for supervisor-mode.
-
-@item sstc
-@tab 1.0
-@tab Supervisor-mode timer interrupts extension.
-
-@item svade
-@tab 1.0
-@tab Cause exception when hardware updating of A/D bits is disabled
-
-@item svadu
-@tab 1.0
-@tab Hardware Updating of A/D Bits extension.
-
-@item svinval
-@tab 1.0
-@tab Fine-grained address-translation cache invalidation extension.
-
-@item svnapot
-@tab 1.0
-@tab NAPOT translation contiguity extension.
-
-@item svpbmt
-@tab 1.0
-@tab Page-based memory types extension.
-
-@item xcvmac
-@tab 1.0
-@tab Core-V multiply-accumulate extension.
-
-@item xcvalu
-@tab 1.0
-@tab Core-V miscellaneous ALU extension.
-
-@item xcvelw
-@tab 1.0
-@tab Core-V event load word extension.
-
-@item xtheadba
-@tab 1.0
-@tab T-head address calculation extension.
-
-@item xtheadbb
-@tab 1.0
-@tab T-head basic bit-manipulation extension.
-
-@item xtheadbs
-@tab 1.0
-@tab T-head single-bit instructions extension.
-
-@item xtheadcmo
-@tab 1.0
-@tab T-head cache management operations extension.
-
-@item xtheadcondmov
-@tab 1.0
-@tab T-head conditional move extension.
-
-@item xtheadfmemidx
-@tab 1.0
-@tab T-head indexed memory operations for floating-point registers extension.
-
-@item xtheadfmv
-@tab 1.0
-@tab T-head double floating-point high-bit data transmission extension.
-
-@item xtheadint
-@tab 1.0
-@tab T-head acceleration interruption extension.
-
-@item xtheadmac
-@tab 1.0
-@tab T-head multiply-accumulate extension.
-
-@item xtheadmemidx
-@tab 1.0
-@tab T-head indexed memory operation extension.
-
-@item xtheadmempair
-@tab 1.0
-@tab T-head two-GPR memory operation extension.
-
-@item xtheadsync
-@tab 1.0
-@tab T-head multi-core synchronization extension.
-
-@item xventanacondops
-@tab 1.0
-@tab Ventana integer conditional operations extension.
-
-@end multitable
+@include riscv-ext.texi
When @option{-march=} is not specified, use the setting from @option{-mcpu}.
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
new file mode 100644
index 000000000000..5ce19b248eb4
--- /dev/null
+++ b/gcc/doc/riscv-ext.texi
@@ -0,0 +1,629 @@
+@c Copyright (C) 2025 Free Software Foundation, Inc.
+@c This is part of the GCC manual.
+@c For copying conditions, see the file gcc/doc/include/fdl.texi.
+
+@c This file is generated automatically using
+@c gcc/config/riscv/gen-riscv-ext-texi.cc from:
+@c gcc/config/riscv/riscv-ext.def
+@c gcc/config/riscv/riscv-opts.h
+
+@c Please *DO NOT* edit manually.
+
+@multitable @columnfractions .10 .10 .80
+@headitem Extension Name @tab Supported Version @tab Description
+
+@item g
+@tab -
+@tab General-purpose computing base extension, @samp{g} will expand to
+@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and
+@samp{zifencei}.
+
+@item e
+@tab 2.0
+@tab Reduced base integer extension
+
+@item i
+@tab 2.0 2.1
+@tab Base integer extension
+
+@item m
+@tab 2.0
+@tab Integer multiplication and division extension
+
+@item a
+@tab 2.0 2.1
+@tab Atomic extension
+
+@item f
+@tab 2.0 2.2
+@tab Single-precision floating-point extension
+
+@item d
+@tab 2.0 2.2
+@tab Double-precision floating-point extension
+
+@item c
+@tab 2.0
+@tab Compressed extension
+
+@item b
+@tab 1.0
+@tab b extension
+
+@item v
+@tab 1.0
+@tab Vector extension
+
+@item h
+@tab 1.0
+@tab Hypervisor extension
+
+@item zic64b
+@tab 1.0
+@tab Cache block size isf 64 bytes
+
+@item zicbom
+@tab 1.0
+@tab Cache-block management extension
+
+@item zicbop
+@tab 1.0
+@tab Cache-block prefetch extension
+
+@item zicboz
+@tab 1.0
+@tab Cache-block zero extension
+
+@item ziccamoa
+@tab 1.0
+@tab Main memory supports all atomics in A
+
+@item ziccif
+@tab 1.0
+@tab Main memory supports instruction fetch with atomicity requirement
+
+@item zicclsm
+@tab 1.0
+@tab Main memory supports misaligned loads/stores
+
+@item ziccrse
+@tab 1.0
+@tab Main memory supports forward progress on LR/SC sequences
+
+@item zicfilp
+@tab 1.0
+@tab zicfilp extension
+
+@item zicfiss
+@tab 1.0
+@tab zicfiss extension
+
+@item zicntr
+@tab 2.0
+@tab Standard extension for base counters and timers
+
+@item zicond
+@tab 1.0
+@tab Integer conditional operations extension
+
+@item zicsr
+@tab 2.0
+@tab Control and status register access extension
+
+@item zifencei
+@tab 2.0
+@tab Instruction-fetch fence extension
+
+@item zihintntl
+@tab 1.0
+@tab Non-temporal locality hints extension
+
+@item zihintpause
+@tab 2.0
+@tab Pause hint extension
+
+@item zihpm
+@tab 2.0
+@tab Standard extension for hardware performance counters
+
+@item zimop
+@tab 1.0
+@tab zimop extension
+
+@item zmmul
+@tab 1.0
+@tab Integer multiplication extension
+
+@item za128rs
+@tab 1.0
+@tab Reservation set size of 128 bytes
+
+@item za64rs
+@tab 1.0
+@tab Reservation set size of 64 bytes
+
+@item zaamo
+@tab 1.0
+@tab zaamo extension
+
+@item zabha
+@tab 1.0
+@tab zabha extension
+
+@item zacas
+@tab 1.0
+@tab zacas extension
+
+@item zalrsc
+@tab 1.0
+@tab zalrsc extension
+
+@item zawrs
+@tab 1.0
+@tab Wait-on-reservation-set extension
+
+@item zama16b
+@tab 1.0
+@tab Zama16b extension, Misaligned loads, stores, and AMOs to main memory
regions that do not cross a naturally aligned 16-byte boundary are atomic.
+
+@item zfa
+@tab 1.0
+@tab Additional floating-point extension
+
+@item zfbfmin
+@tab 1.0
+@tab zfbfmin extension
+
+@item zfh
+@tab 1.0
+@tab Half-precision floating-point extension
+
+@item zfhmin
+@tab 1.0
+@tab Minimal half-precision floating-point extension
+
+@item zfinx
+@tab 1.0
+@tab Single-precision floating-point in integer registers extension
+
+@item zdinx
+@tab 1.0
+@tab Double-precision floating-point in integer registers extension
+
+@item zca
+@tab 1.0
+@tab Integer compressed instruction extension
+
+@item zcb
+@tab 1.0
+@tab Simple compressed instruction extension
+
+@item zcd
+@tab 1.0
+@tab Compressed double-precision floating point loads and stores extension
+
+@item zce
+@tab 1.0
+@tab Compressed instruction extensions for embedded processors
+
+@item zcf
+@tab 1.0
+@tab Compressed single-precision floating point loads and stores extension
+
+@item zcmop
+@tab 1.0
+@tab zcmop extension
+
+@item zcmp
+@tab 1.0
+@tab Compressed push pop extension
+
+@item zcmt
+@tab 1.0
+@tab Table jump instruction extension
+
+@item zba
+@tab 1.0
+@tab Address calculation extension
+
+@item zbb
+@tab 1.0
+@tab Basic bit manipulation extension
+
+@item zbc
+@tab 1.0
+@tab Carry-less multiplication extension
+
+@item zbkb
+@tab 1.0
+@tab Cryptography bit-manipulation extension
+
+@item zbkc
+@tab 1.0
+@tab Cryptography carry-less multiply extension
+
+@item zbkx
+@tab 1.0
+@tab Cryptography crossbar permutation extension
+
+@item zbs
+@tab 1.0
+@tab Single-bit operation extension
+
+@item zk
+@tab 1.0
+@tab Standard scalar cryptography extension
+
+@item zkn
+@tab 1.0
+@tab NIST algorithm suite extension
+
+@item zknd
+@tab 1.0
+@tab AES Decryption extension
+
+@item zkne
+@tab 1.0
+@tab AES Encryption extension
+
+@item zknh
+@tab 1.0
+@tab Hash function extension
+
+@item zkr
+@tab 1.0
+@tab Entropy source extension
+
+@item zks
+@tab 1.0
+@tab ShangMi algorithm suite extension
+
+@item zksed
+@tab 1.0
+@tab SM4 block cipher extension
+
+@item zksh
+@tab 1.0
+@tab SM3 hash function extension
+
+@item zkt
+@tab 1.0
+@tab Data independent execution latency extension
+
+@item ztso
+@tab 1.0
+@tab Total store ordering extension
+
+@item zvbb
+@tab 1.0
+@tab Vector basic bit-manipulation extension
+
+@item zvbc
+@tab 1.0
+@tab Vector carryless multiplication extension
+
+@item zve32f
+@tab 1.0
+@tab Vector extensions for embedded processors
+
+@item zve32x
+@tab 1.0
+@tab Vector extensions for embedded processors
+
+@item zve64d
+@tab 1.0
+@tab Vector extensions for embedded processors
+
+@item zve64f
+@tab 1.0
+@tab Vector extensions for embedded processors
+
+@item zve64x
+@tab 1.0
+@tab Vector extensions for embedded processors
+
+@item zvfbfmin
+@tab 1.0
+@tab Vector BF16 converts extension
+
+@item zvfbfwma
+@tab 1.0
+@tab zvfbfwma extension
+
+@item zvfh
+@tab 1.0
+@tab Vector half-precision floating-point extension
+
+@item zvfhmin
+@tab 1.0
+@tab Vector minimal half-precision floating-point extension
+
+@item zvkb
+@tab 1.0
+@tab Vector cryptography bit-manipulation extension
+
+@item zvkg
+@tab 1.0
+@tab Vector GCM/GMAC extension
+
+@item zvkn
+@tab 1.0
+@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to
+
+@item zvknc
+@tab 1.0
+@tab Vector NIST Algorithm Suite with carryless multiply extension,
@samp{zvknc}
+
+@item zvkned
+@tab 1.0
+@tab Vector AES block cipher extension
+
+@item zvkng
+@tab 1.0
+@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand
+
+@item zvknha
+@tab 1.0
+@tab Vector SHA-2 secure hash extension
+
+@item zvknhb
+@tab 1.0
+@tab Vector SHA-2 secure hash extension
+
+@item zvks
+@tab 1.0
+@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand
+
+@item zvksc
+@tab 1.0
+@tab Vector ShangMi algorithm suite with carryless multiplication extension,
+
+@item zvksed
+@tab 1.0
+@tab Vector SM4 Block Cipher extension
+
+@item zvksg
+@tab 1.0
+@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will
expand
+
+@item zvksh
+@tab 1.0
+@tab Vector SM3 Secure Hash extension
+
+@item zvkt
+@tab 1.0
+@tab Vector data independent execution latency extension
+
+@item zvl1024b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl128b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl16384b
+@tab 1.0
+@tab zvl16384b extension
+
+@item zvl2048b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl256b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl32768b
+@tab 1.0
+@tab zvl32768b extension
+
+@item zvl32b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl4096b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl512b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl64b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl65536b
+@tab 1.0
+@tab zvl65536b extension
+
+@item zvl8192b
+@tab 1.0
+@tab zvl8192b extension
+
+@item zhinx
+@tab 1.0
+@tab Half-precision floating-point in integer registers extension
+
+@item zhinxmin
+@tab 1.0
+@tab Minimal half-precision floating-point in integer registers extension
+
+@item sdtrig
+@tab 1.0
+@tab sdtrig extension
+
+@item smaia
+@tab 1.0
+@tab Advanced interrupt architecture extension
+
+@item smepmp
+@tab 1.0
+@tab PMP Enhancements for memory access and execution prevention on Machine
mode
+
+@item smmpm
+@tab 1.0
+@tab smmpm extension
+
+@item smnpm
+@tab 1.0
+@tab smnpm extension
+
+@item smstateen
+@tab 1.0
+@tab State enable extension
+
+@item ssaia
+@tab 1.0
+@tab Advanced interrupt architecture extension for supervisor-mode
+
+@item sscofpmf
+@tab 1.0
+@tab Count overflow & filtering extension
+
+@item ssnpm
+@tab 1.0
+@tab ssnpm extension
+
+@item sspm
+@tab 1.0
+@tab sspm extension
+
+@item ssstateen
+@tab 1.0
+@tab State-enable extension for supervisor-mode
+
+@item sstc
+@tab 1.0
+@tab Supervisor-mode timer interrupts extension
+
+@item ssstrict
+@tab 1.0
+@tab ssstrict extension
+
+@item supm
+@tab 1.0
+@tab supm extension
+
+@item svinval
+@tab 1.0
+@tab Fine-grained address-translation cache invalidation extension
+
+@item svnapot
+@tab 1.0
+@tab NAPOT translation contiguity extension
+
+@item svpbmt
+@tab 1.0
+@tab Page-based memory types extension
+
+@item svvptc
+@tab 1.0
+@tab svvptc extension
+
+@item svadu
+@tab 1.0
+@tab Hardware Updating of A/D Bits extension
+
+@item svade
+@tab 1.0
+@tab Cause exception when hardware updating of A/D bits is disabled
+
+@item xcvalu
+@tab 1.0
+@tab Core-V miscellaneous ALU extension
+
+@item xcvbi
+@tab 1.0
+@tab xcvbi extension
+
+@item xcvelw
+@tab 1.0
+@tab Core-V event load word extension
+
+@item xcvmac
+@tab 1.0
+@tab Core-V multiply-accumulate extension
+
+@item xcvsimd
+@tab 1.0
+@tab xcvsimd extension
+
+@item xsfcease
+@tab 1.0
+@tab xsfcease extension
+
+@item xsfvcp
+@tab 1.0
+@tab xsfvcp extension
+
+@item xsfvfnrclipxfqf
+@tab 1.0
+@tab xsfvfnrclipxfqf extension
+
+@item xsfvqmaccdod
+@tab 1.0
+@tab xsfvqmaccdod extension
+
+@item xsfvqmaccqoq
+@tab 1.0
+@tab xsfvqmaccqoq extension
+
+@item xtheadba
+@tab 1.0
+@tab T-head address calculation extension
+
+@item xtheadbb
+@tab 1.0
+@tab T-head basic bit-manipulation extension
+
+@item xtheadbs
+@tab 1.0
+@tab T-head single-bit instructions extension
+
+@item xtheadcmo
+@tab 1.0
+@tab T-head cache management operations extension
+
+@item xtheadcondmov
+@tab 1.0
+@tab T-head conditional move extension
+
+@item xtheadfmemidx
+@tab 1.0
+@tab T-head indexed memory operations for floating-point registers extension
+
+@item xtheadfmv
+@tab 1.0
+@tab T-head double floating-point high-bit data transmission extension
+
+@item xtheadint
+@tab 1.0
+@tab T-head acceleration interruption extension
+
+@item xtheadmac
+@tab 1.0
+@tab T-head multiply-accumulate extension
+
+@item xtheadmemidx
+@tab 1.0
+@tab T-head indexed memory operation extension
+
+@item xtheadmempair
+@tab 1.0
+@tab T-head two-GPR memory operation extension
+
+@item xtheadsync
+@tab 1.0
+@tab T-head multi-core synchronization extension
+
+@item xtheadvector
+@tab 1.0
+@tab xtheadvector extension
+
+@item xventanacondops
+@tab 1.0
+@tab Ventana integer conditional operations extension
+
+@end multitable
--
2.34.1
