From: Pan Li <pan2...@intel.com>

Add asm dump check test for vec_duplicate + vrsub.vv combine to vrsub.vx.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Add asm check
        for vrsub with GR2VR cost is 15.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c  | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c  | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index aa21e10130b..b5f36ff3a44 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(int16_t, +, add)
 DEF_VX_BINARY_CASE_0(int16_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int16_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 7c374694321..93ba98d57e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(int32_t, +, add)
 DEF_VX_BINARY_CASE_0(int32_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int32_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 3efb0d7e92e..e73fbce0106 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(int64_t, +, add)
 DEF_VX_BINARY_CASE_0(int64_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int64_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index d823ed9cc9a..2a3a6f1884b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(int8_t, +, add)
 DEF_VX_BINARY_CASE_0(int8_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int8_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 1ab09c8d78e..63358cd3354 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(uint16_t, +, add)
 DEF_VX_BINARY_CASE_0(uint16_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint16_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 9247db70154..6ed098773c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(uint32_t, +, add)
 DEF_VX_BINARY_CASE_0(uint32_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint32_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 139996b6742..f2bfe28f1a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(uint64_t, +, add)
 DEF_VX_BINARY_CASE_0(uint64_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint64_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index d439dc3d8b7..a89d4a00268 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -5,6 +5,8 @@
 
 DEF_VX_BINARY_CASE_0(uint8_t, +, add)
 DEF_VX_BINARY_CASE_0(uint8_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint8_t, -, rsub);
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
+/* { dg-final { scan-assembler-not {vrsub.vx} } } */
-- 
2.43.0

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