From: Pan Li <pan2...@intel.com>
Add asm dump check and run test for vec_duplicate + vrsub.vv combine to
vrsub.vx.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add vrsub asm check.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test helper
macros for vx binary reversed.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for vrsub.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../riscv/rvv/autovec/vx_vf/vx-1-i16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx_binary.h | 63 +++
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 392 ++++++++++++++++++
.../rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c | 15 +
.../rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c | 15 +
.../rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c | 15 +
.../rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c | 15 +
.../rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c | 15 +
.../rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c | 15 +
.../rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c | 15 +
.../rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c | 15 +
18 files changed, 591 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index c6b25f1b857..015b0866668 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -5,6 +5,8 @@
DEF_VX_BINARY_CASE_0(int16_t, +, add)
DEF_VX_BINARY_CASE_0(int16_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int16_t, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index cb4ccfa1790..f0a88e8da87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -5,6 +5,8 @@
DEF_VX_BINARY_CASE_0(int32_t, +, add)
DEF_VX_BINARY_CASE_0(int32_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int32_t, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index bf249846452..fbf9f6a930f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -5,6 +5,8 @@
DEF_VX_BINARY_CASE_0(int64_t, +, add)
DEF_VX_BINARY_CASE_0(int64_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int64_t, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index e830c753ae8..55309308573 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -5,6 +5,8 @@
DEF_VX_BINARY_CASE_0(int8_t, +, add)
DEF_VX_BINARY_CASE_0(int8_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(int8_t, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index f08305e8256..15edd71a438 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -5,6 +5,8 @@
DEF_VX_BINARY_CASE_0(uint16_t, +, add)
DEF_VX_BINARY_CASE_0(uint16_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint16_t, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 1a7ae1f1c78..992083e7235 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -5,6 +5,8 @@
DEF_VX_BINARY_CASE_0(uint32_t, +, add)
DEF_VX_BINARY_CASE_0(uint32_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint32_t, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index d478cafa0fe..bb445f6e0ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -5,6 +5,8 @@
DEF_VX_BINARY_CASE_0(uint64_t, +, add)
DEF_VX_BINARY_CASE_0(uint64_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint64_t, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index aa3f5b79d31..73e144b06ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -5,6 +5,8 @@
DEF_VX_BINARY_CASE_0(uint8_t, +, add)
DEF_VX_BINARY_CASE_0(uint8_t, -, sub)
+DEF_VX_BINARY_REVERSE_CASE_0(uint8_t, -, rsub);
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index f46210924ea..66e238c903a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -18,6 +18,22 @@ test_vx_binary_##NAME##_##T##_case_0 (T * restrict out, T *
restrict in, \
#define RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) \
RUN_VX_BINARY_CASE_0(T, NAME, out, in, x, n)
+#define DEF_VX_BINARY_REVERSE_CASE_0(T, OP, NAME) \
+void \
+test_vx_binary_reverse_##NAME##_##T##_case_0 (T * restrict out, \
+ T * restrict in, T x, \
+ unsigned n) \
+{ \
+ for (unsigned i = 0; i < n; i++) \
+ out[i] = x OP in[i]; \
+}
+#define DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, OP, NAME) \
+ DEF_VX_BINARY_REVERSE_CASE_0(T, OP, NAME)
+#define RUN_VX_BINARY_REVERSE_CASE_0(T, NAME, out, in, x, n) \
+ test_vx_binary_reverse_##NAME##_##T##_case_0(out, in, x, n)
+#define RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) \
+ RUN_VX_BINARY_REVERSE_CASE_0(T, NAME, out, in, x, n)
+
#define VX_BINARY_BODY(op) \
out[k + 0] = in[k + 0] op tmp; \
out[k + 1] = in[k + 1] op tmp; \
@@ -64,4 +80,51 @@ test_vx_binary_##NAME##_##T##_case_1 (T * restrict out, T *
restrict in, \
#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, NAME, BODY) \
DEF_VX_BINARY_CASE_1(T, OP, NAME, BODY)
+#define VX_BINARY_REVERSE_BODY(op) \
+ out[k + 0] = tmp op in[k + 0]; \
+ out[k + 1] = tmp op in[k + 1]; \
+ k += 2;
+
+#define VX_BINARY_REVERSE_BODY_X4(op) \
+ VX_BINARY_REVERSE_BODY(op) \
+ VX_BINARY_REVERSE_BODY(op)
+
+#define VX_BINARY_REVERSE_BODY_X8(op) \
+ VX_BINARY_REVERSE_BODY_X4(op) \
+ VX_BINARY_REVERSE_BODY_X4(op)
+
+#define VX_BINARY_REVERSE_BODY_X16(op) \
+ VX_BINARY_REVERSE_BODY_X8(op) \
+ VX_BINARY_REVERSE_BODY_X8(op)
+
+#define VX_BINARY_REVERSE_BODY_X32(op) \
+ VX_BINARY_REVERSE_BODY_X16(op) \
+ VX_BINARY_REVERSE_BODY_X16(op)
+
+#define VX_BINARY_REVERSE_BODY_X64(op) \
+ VX_BINARY_REVERSE_BODY_X32(op) \
+ VX_BINARY_REVERSE_BODY_X32(op)
+
+#define VX_BINARY_REVERSE_BODY_X128(op) \
+ VX_BINARY_REVERSE_BODY_X64(op) \
+ VX_BINARY_REVERSE_BODY_X64(op)
+
+#define DEF_VX_BINARY_REVERSE_CASE_1(T, OP, NAME, BODY) \
+void \
+test_vx_binary_reverse_##NAME##_##T##_case_1 (T * restrict out, \
+ T * restrict in, \
+ T x, unsigned n) \
+{ \
+ unsigned k = 0; \
+ T tmp = x + 3; \
+ \
+ while (k < n) \
+ { \
+ tmp = tmp ^ 0x3f; \
+ BODY(OP) \
+ } \
+}
+#define DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, OP, NAME, BODY) \
+ DEF_VX_BINARY_REVERSE_CASE_1(T, OP, NAME, BODY)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 7e68db92ef8..08d53b28ec5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -790,4 +790,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, sub)[][3][N] =
},
};
+int8_t TEST_BINARY_DATA(int8_t, rsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { 127 },
+ {
+ 127, 127, 127, 127,
+ 126, 126, 126, 126,
+ 1, 1, 1, 1,
+ 125, 125, 125, 125,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 126, 126, 126, 126,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { -128 },
+ {
+ -128, -128, -128, -128,
+ -127, -127, -127, -127,
+ -1, -1, -1, -1,
+ -126, -126, -126, -126,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -127, -127, -127, -127,
+ -2, -2, -2, -2,
+ },
+ },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, rsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { 32767 },
+ {
+ 32767, 32767, 32767, 32767,
+ 32766, 32766, 32766, 32766,
+ 1, 1, 1, 1,
+ 32765, 32765, 32765, 32765,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 32766, 32766, 32766, 32766,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { -32768 },
+ {
+ -32768, -32768, -32768, -32768,
+ -32767, -32767, -32767, -32767,
+ -1, -1, -1, -1,
+ -32766, -32766, -32766, -32766,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -32767, -32767, -32767, -32767,
+ -2, -2, -2, -2,
+ },
+ },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, rsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { 2147483647 },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483646, 2147483646, 2147483646, 2147483646,
+ 1, 1, 1, 1,
+ 2147483645, 2147483645, 2147483645, 2147483645,
+ },
+ {
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 2147483646, 2147483646, 2147483646, 2147483646,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { -2147483648 },
+ {
+ -2147483648, -2147483648, -2147483648, -2147483648,
+ -2147483647, -2147483647, -2147483647, -2147483647,
+ -1, -1, -1, -1,
+ -2147483646, -2147483646, -2147483646, -2147483646,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ -2147483647, -2147483647, -2147483647, -2147483647,
+ -2, -2, -2, -2,
+ },
+ },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, rsub)[][3][N] =
+{
+ {
+ { 1 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ },
+ {
+ 0, 0, 0, 0,
+ -1, -1, -1, -1,
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { 9223372036854775807ll },
+ {
+ 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll,
9223372036854775807ll,
+ 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll,
9223372036854775806ll,
+ 1, 1, 1,
1,
+ 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll,
9223372036854775805ll,
+ },
+ {
+ 0, 0,
0, 0,
+ 1, 1,
1, 1,
+ 9223372036854775806ull, 9223372036854775806ull,
9223372036854775806ull, 9223372036854775806ull,
+ 2, 2,
2, 2,
+ },
+ },
+ {
+ { -9223372036854775808ull },
+ {
+ -9223372036854775808ull, -9223372036854775808ull,
-9223372036854775808ull, -9223372036854775808ull,
+ -9223372036854775807ll, -9223372036854775807ll,
-9223372036854775807ll, -9223372036854775807ll,
+ -1, -1,
-1, -1,
+ -9223372036854775806ll, -9223372036854775806ll,
-9223372036854775806ll, -9223372036854775806ll,
+ },
+ {
+ 0, 0, 0,
0,
+ -1, -1, -1,
-1,
+ -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll,
-9223372036854775807ll,
+ -2, -2, -2,
-2,
+ },
+ },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, rsub)[][3][N] =
+{
+ {
+ { 12 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 12, 12, 12, 12,
+ 10, 10, 10, 10,
+ },
+ {
+ 11, 11, 11, 11,
+ 10, 10, 10, 10,
+ 0, 0, 0, 0,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { 127 },
+ {
+ 127, 127, 127, 127,
+ 28, 28, 28, 28,
+ 4, 4, 4, 4,
+ 5, 5, 5, 5,
+ },
+ {
+ 0, 0, 0, 0,
+ 99, 99, 99, 99,
+ 123, 123, 123, 123,
+ 122, 122, 122, 122,
+ },
+ },
+ {
+ { 255 },
+ {
+ 253, 253, 253, 253,
+ 254, 254, 254, 254,
+ 255, 255, 255, 255,
+ 252, 252, 252, 252,
+ },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 3, 3, 3, 3,
+ },
+ },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, rsub)[][3][N] =
+{
+ {
+ { 12 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 12, 12, 12, 12,
+ 10, 10, 10, 10,
+ },
+ {
+ 11, 11, 11, 11,
+ 10, 10, 10, 10,
+ 0, 0, 0, 0,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { 32768 },
+ {
+ 32767, 32767, 32767, 32767,
+ 32768, 32768, 32768, 32768,
+ 4, 4, 4, 4,
+ 5, 5, 5, 5,
+ },
+ {
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 32764, 32764, 32764, 32764,
+ 32763, 32763, 32763, 32763,
+ },
+ },
+ {
+ { 65535 },
+ {
+ 65533, 65533, 65533, 65533,
+ 65534, 65534, 65534, 65534,
+ 65535, 65535, 65535, 65535,
+ 65532, 65532, 65532, 65532,
+ },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 3, 3, 3, 3,
+ },
+ },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, rsub)[][3][N] =
+{
+ {
+ { 12 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 12, 12, 12, 12,
+ 10, 10, 10, 10,
+ },
+ {
+ 11, 11, 11, 11,
+ 10, 10, 10, 10,
+ 0, 0, 0, 0,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { 2147483648 },
+ {
+ 2147483647, 2147483647, 2147483647, 2147483647,
+ 2147483648, 2147483648, 2147483648, 2147483648,
+ 4, 4, 4, 4,
+ 5, 5, 5, 5,
+ },
+ {
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 2147483644, 2147483644, 2147483644, 2147483644,
+ 2147483643, 2147483643, 2147483643, 2147483643,
+ },
+ },
+ {
+ { 4294967295 },
+ {
+ 4294967293, 4294967293, 4294967293, 4294967293,
+ 4294967294, 4294967294, 4294967294, 4294967294,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967292, 4294967292, 4294967292, 4294967292,
+ },
+ {
+ 2, 2, 2, 2,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0,
+ 3, 3, 3, 3,
+ },
+ },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, rsub)[][3][N] =
+{
+ {
+ { 12 },
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 12, 12, 12, 12,
+ 10, 10, 10, 10,
+ },
+ {
+ 11, 11, 11, 11,
+ 10, 10, 10, 10,
+ 0, 0, 0, 0,
+ 2, 2, 2, 2,
+ },
+ },
+ {
+ { 9223372036854775808ull },
+ {
+ 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull,
+ 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull,
9223372036854775808ull,
+ 4ull, 4ull, 4ull,
4ull,
+ 5ull, 5ull, 5ull,
5ull,
+ },
+ {
+ 1, 1, 1,
1,
+ 0, 0, 0,
0,
+ 9223372036854775804ull, 9223372036854775804ull, 9223372036854775804ull,
9223372036854775804ull,
+ 9223372036854775803ull, 9223372036854775803ull, 9223372036854775803ull,
9223372036854775803ull,
+ },
+ },
+ {
+ { 18446744073709551615ull },
+ {
+ 18446744073709551613ull, 18446744073709551613ull,
18446744073709551613ull, 18446744073709551613ull,
+ 18446744073709551614ull, 18446744073709551614ull,
18446744073709551614ull, 18446744073709551614ull,
+ 18446744073709551615ull, 18446744073709551615ull,
18446744073709551615ull, 18446744073709551615ull,
+ 18446744073709551612ull, 18446744073709551612ull,
18446744073709551612ull, 18446744073709551612ull,
+ },
+ {
+ 2, 2,
2, 2,
+ 1, 1,
1, 1,
+ 0, 0,
0, 0,
+ 3, 3,
3, 3,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c
new file mode 100644
index 00000000000..65ce6a1a6c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int16_t
+#define NAME rsub
+
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T,
NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c
new file mode 100644
index 00000000000..170779c3c2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+#define NAME rsub
+
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T,
NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c
new file mode 100644
index 00000000000..796cfdfb391
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int64_t
+#define NAME rsub
+
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T,
NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c
new file mode 100644
index 00000000000..0419e59c92d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int8_t
+#define NAME rsub
+
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T,
NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c
new file mode 100644
index 00000000000..bf9f6ceb7b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint16_t
+#define NAME rsub
+
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T,
NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c
new file mode 100644
index 00000000000..afe037dde54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint32_t
+#define NAME rsub
+
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T,
NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c
new file mode 100644
index 00000000000..5d4c01e92b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint64_t
+#define NAME rsub
+
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T,
NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c
new file mode 100644
index 00000000000..43d785f3bd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint8_t
+#define NAME rsub
+
+DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T,
NAME, out, in, x, n)
+
+#include "vx_binary_run.h"
--
2.43.0
