This patch add the RISC-V Shlcofideleg extension. It supports delegating LCOFI interrupts(the count-overflow interrupts) to VS-mode.[1]
[1] https://riscv.github.io/riscv-isa-manual/snapshot/privileged gcc/ChangeLog: * config/riscv/riscv-ext.def: New extension defs. * config/riscv/riscv-ext.opt: Ditto. * doc/riscv-ext.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-57.c: New test. Signed-off-by: Jiawei <jia...@iscas.ac.cn> --- gcc/config/riscv/riscv-ext.def | 13 +++++++++++++ gcc/config/riscv/riscv-ext.opt | 2 ++ gcc/doc/riscv-ext.texi | 4 ++++ gcc/testsuite/gcc.target/riscv/arch-57.c | 5 +++++ 4 files changed, 24 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-57.c diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index 97b576617ad..1b5dce29b15 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -1610,6 +1610,19 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ shlcofideleg, + /* UPPERCAE_NAME */ SHLCOFIDELEG, + /* FULL_NAME */ "Delegating LCOFI interrupts to VS-mode", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"h"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sh, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + DEFINE_RISCV_EXT( /* NAME */ shtvala, /* UPPERCAE_NAME */ SHTVALA, diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index 9199aa31b42..6868e79987c 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -325,6 +325,8 @@ Mask(SHCOUNTERENW) Var(riscv_sh_subext) Mask(SHGATPA) Var(riscv_sh_subext) +Mask(SHLCOFIDELEG) Var(riscv_sh_subext) + Mask(SHTVALA) Var(riscv_sh_subext) Mask(SHVSTVALA) Var(riscv_sh_subext) diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index bd3d29c75ab..4b92b8d75db 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -474,6 +474,10 @@ @tab 1.0 @tab SvNNx4 mode supported for all modes supported by satp +@item shlcofideleg +@tab 1.0 +@tab Delegating LCOFI interrupts to VS-mode + @item shtvala @tab 1.0 @tab The htval register provides all needed values diff --git a/gcc/testsuite/gcc.target/riscv/arch-57.c b/gcc/testsuite/gcc.target/riscv/arch-57.c new file mode 100644 index 00000000000..de9f9fc6e53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-57.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_shlcofideleg -mabi=lp64" } */ +int foo() +{ +} -- 2.43.0
