From: Yunze Zhu <yunze...@linux.alibaba.com>
This commit add support for xtheadvector-specific unit-stride segment
load/store intrinsics with b/h/w suffix. We also defined enum to be used
in thead-vector-builtins-bases.cc
https://github.com/XUANTIE-RV/thead-extension-spec/pull/66
gcc/ChangeLog:
* config.gcc: Add new Thead *.o files.
* config/riscv/riscv-vector-builtins-shapes.cc (struct
th_seg_loadstore_def):
Define new builtin shapes.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_TH_INT_TUPLE_OPS):
New type.
(DEF_RVV_TH_UINT_TUPLE_OPS):Ditto.
(vint8m1x2_t):Ditto.
(vint8m1x3_t):Ditto.
(vint8m1x4_t):Ditto.
(vint8m1x5_t):Ditto.
(vint8m1x6_t):Ditto.
(vint8m1x7_t):Ditto.
(vint8m1x8_t):Ditto.
(vint8m2x2_t):Ditto.
(vint8m2x3_t):Ditto.
(vint8m2x4_t):Ditto.
(vint8m4x2_t):Ditto.
(vint16m1x2_t):Ditto.
(vint16m1x3_t):Ditto.
(vint16m1x4_t):Ditto.
(vint16m1x5_t):Ditto.
(vint16m1x6_t):Ditto.
(vint16m1x7_t):Ditto.
(vint16m1x8_t):Ditto.
(vint16m2x2_t):Ditto.
(vint16m2x3_t):Ditto.
(vint16m2x4_t):Ditto.
(vint16m4x2_t):Ditto.
(vint32m1x2_t):Ditto.
(vint32m1x3_t):Ditto.
(vint32m1x4_t):Ditto.
(vint32m1x5_t):Ditto.
(vint32m1x6_t):Ditto.
(vint32m1x7_t):Ditto.
(vint32m1x8_t):Ditto.
(vint32m2x2_t):Ditto.
(vint32m2x3_t):Ditto.
(vint32m2x4_t):Ditto.
(vint32m4x2_t):Ditto.
(vuint8m1x2_t):Ditto.
(vuint8m1x3_t):Ditto.
(vuint8m1x4_t):Ditto.
(vuint8m1x5_t):Ditto.
(vuint8m1x6_t):Ditto.
(vuint8m1x7_t):Ditto.
(vuint8m1x8_t):Ditto.
(vuint8m2x2_t):Ditto.
(vuint8m2x3_t):Ditto.
(vuint8m2x4_t):Ditto.
(vuint8m4x2_t):Ditto.
(vuint16m1x2_t):Ditto.
(vuint16m1x3_t):Ditto.
(vuint16m1x4_t):Ditto.
(vuint16m1x5_t):Ditto.
(vuint16m1x6_t):Ditto.
(vuint16m1x7_t):Ditto.
(vuint16m1x8_t):Ditto.
(vuint16m2x2_t):Ditto.
(vuint16m2x3_t):Ditto.
(vuint16m2x4_t):Ditto.
(vuint16m4x2_t):Ditto.
(vuint32m1x2_t):Ditto.
(vuint32m1x3_t):Ditto.
(vuint32m1x4_t):Ditto.
(vuint32m1x5_t):Ditto.
(vuint32m1x6_t):Ditto.
(vuint32m1x7_t):Ditto.
(vuint32m1x8_t):Ditto.
(vuint32m2x2_t):Ditto.
(vuint32m2x3_t):Ditto.
(vuint32m2x4_t):Ditto.
(vuint32m4x2_t):Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_TH_INT_TUPLE_OPS):New
builtins def.
(DEF_RVV_TH_UINT_TUPLE_OPS):Ditto.
* config/riscv/t-riscv:Add include for Thead files.
* config/riscv/thead-vector-builtins-functions.def (th_vlseg):New
intrinsics def.
(th_vlsegu):Ditto.
(th_vsseg):Ditto.
* config/riscv/thead-vector.md
(@pred_th_unit_seg_load<vlmem_op_attr><mode>):New RTL mode.
(@pred_th_unit_seg_store<vlmem_op_attr><mode>):Ditto.
* config/riscv/thead.cc (th_asm_output_opcode):Implement Thead function
to add assembler insn code prefix/suffix.
* config/riscv/thead-vector-builtins-bases.cc: New file.
* config/riscv/thead-vector-builtins-bases.h: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/vlseg-vsseg.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vlsegu-vsseg.c: New test.
---
gcc/config.gcc | 2 +-
.../riscv/riscv-vector-builtins-shapes.cc | 62 ++++++++
.../riscv/riscv-vector-builtins-shapes.h | 2 +
.../riscv/riscv-vector-builtins-types.def | 82 +++++++++++
gcc/config/riscv/riscv-vector-builtins.cc | 44 ++++++
gcc/config/riscv/t-riscv | 19 +++
.../riscv/thead-vector-builtins-bases.cc | 138 ++++++++++++++++++
.../riscv/thead-vector-builtins-bases.h | 36 +++++
.../riscv/thead-vector-builtins-functions.def | 4 +
gcc/config/riscv/thead-vector.md | 133 +++++++++++++++++
gcc/config/riscv/thead.cc | 68 ++++++---
.../riscv/rvv/xtheadvector/vlseg-vsseg.c | 118 +++++++++++++++
.../riscv/rvv/xtheadvector/vlsegu-vsseg.c | 116 +++++++++++++++
13 files changed, 799 insertions(+), 25 deletions(-)
create mode 100644 gcc/config/riscv/thead-vector-builtins-bases.cc
create mode 100644 gcc/config/riscv/thead-vector-builtins-bases.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlseg-vsseg.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlsegu-vsseg.c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 1e386a469e0..0cdacc4de65 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -549,7 +549,7 @@ riscv*)
cpu_type=riscv
extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o
riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o"
extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o
riscv-avlprop.o riscv-vect-permconst.o"
- extra_objs="${extra_objs} riscv-vector-builtins.o
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o
sifive-vector-builtins-bases.o"
+ extra_objs="${extra_objs} riscv-vector-builtins.o
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o
sifive-vector-builtins-bases.o thead-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o"
d_target_objs="riscv-d.o"
extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h
riscv_th_vector.h sifive_vector.h"
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index b855d4c5fa5..c6a10c2e5fa 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -1389,6 +1389,67 @@ struct sf_vcix_def : public build_base
};
+/* th_seg_loadstore_def class. */
+struct th_seg_loadstore_def : public build_base {
+
+ char *get_name (function_builder &b, const function_instance &instance,
+ bool overloaded_p) const override {
+ /* Return nullptr if it can not be overloaded. */
+ if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
+ return nullptr;
+
+ if (strstr (instance.base_name, "vlseg"))
+ b.append_name ("__riscv_th_vlseg");
+ else if (strstr (instance.base_name, "vsseg"))
+ b.append_name ("__riscv_th_vsseg");
+ else
+ gcc_unreachable ();
+
+ tree type = builtin_types[instance.type.index].vector;
+ machine_mode mode = TYPE_MODE (type);
+
+ int nf = get_nf (mode);
+ int sew = GET_MODE_BITSIZE (GET_MODE_INNER (get_subpart_mode (mode)));
+ /* vop --> vop<nf>. */
+ b.append_nf (nf);
+
+ /* vop<nf> --> vop<nf><b/h/w>. */
+ switch (sew)
+ {
+ case 8:
+ b.append_name ("b");
+ break;
+ case 16:
+ b.append_name ("h");
+ break;
+ case 32:
+ b.append_name ("w");
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ if (strstr (instance.base_name, "l")
+ && TYPE_UNSIGNED ( (builtin_types[instance.type.index].scalar)))
+ b.append_name ("u");
+
+ if (!overloaded_p)
+ {
+ /* vop<nf><b/h/w> --> vop<nf><b/h/w>_v. */
+ b.append_name (operand_suffixes[instance.op_info->op]);
+ /* vop<nf><b/h/w>_v --> vop<nf><b/h/w>_v_<type>. */
+ b.append_name (type_suffixes[instance.type.index].vector);
+ }
+
+ /* According to rvv-intrinsic-doc, it does not add "_m" suffix
+ for vop_m C++ overloaded API. */
+ if (overloaded_p && instance.pred == PRED_TYPE_m)
+ return b.finish_name ();
+ b.append_name (predication_suffixes[instance.pred]);
+ return b.finish_name ();
+ }
+};
+
SHAPE(vsetvl, vsetvl)
SHAPE(vsetvl, vsetvlmax)
SHAPE(loadstore, loadstore)
@@ -1427,4 +1488,5 @@ SHAPE (sf_vqmacc, sf_vqmacc)
SHAPE (sf_vfnrclip, sf_vfnrclip)
SHAPE(sf_vcix_se, sf_vcix_se)
SHAPE(sf_vcix, sf_vcix)
+SHAPE (th_seg_loadstore, th_seg_loadstore)
} // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.h
b/gcc/config/riscv/riscv-vector-builtins-shapes.h
index 2f2636ee386..f432d9edbff 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.h
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.h
@@ -64,6 +64,8 @@ extern const function_shape *const sf_vqmacc;
extern const function_shape *const sf_vfnrclip;
extern const function_shape *const sf_vcix_se;
extern const function_shape *const sf_vcix;
+/* Xtheadvector extension. */
+extern const function_shape *const th_seg_loadstore;
}
} // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def
b/gcc/config/riscv/riscv-vector-builtins-types.def
index ade6644b56e..2597a3501e0 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -381,6 +381,18 @@ along with GCC; see the file COPYING3. If not see
#define DEF_RVV_X2_WU_OPS(TYPE, REQUIRE)
#endif
+/* Use "DEF_RVV_TH_INT_TUPLE_OPS" macro include all signed tuple types
+ which will be iterated and registered as intrinsic functions. */
+#ifndef DEF_RVV_TH_INT_TUPLE_OPS
+#define DEF_RVV_TH_INT_TUPLE_OPS(TYPE, REQUIRE)
+#endif
+
+/* Use "DEF_RVV_TH_UINT_TUPLE_OPS" macro include all unsigned tuple types
+ which will be iterated and registered as intrinsic functions. */
+#ifndef DEF_RVV_TH_UINT_TUPLE_OPS
+#define DEF_RVV_TH_UINT_TUPLE_OPS(TYPE, REQUIRE)
+#endif
+
DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_I_OPS (vint8mf4_t, 0)
DEF_RVV_I_OPS (vint8mf2_t, 0)
@@ -1501,6 +1513,74 @@ DEF_RVV_X2_WU_OPS (vuint32m1_t, 0)
DEF_RVV_X2_WU_OPS (vuint32m2_t, 0)
DEF_RVV_X2_WU_OPS (vuint32m4_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m1x2_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m1x3_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m1x4_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m1x5_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m1x6_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m1x7_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m1x8_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m2x2_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m2x3_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m2x4_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint8m4x2_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m1x2_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m1x3_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m1x4_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m1x5_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m1x6_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m1x7_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m1x8_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m2x2_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m2x3_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m2x4_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint16m4x2_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m1x2_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m1x3_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m1x4_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m1x5_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m1x6_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m1x7_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m1x8_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m2x2_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m2x3_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m2x4_t, 0)
+DEF_RVV_TH_INT_TUPLE_OPS (vint32m4x2_t, 0)
+
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m1x2_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m1x3_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m1x4_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m1x5_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m1x6_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m1x7_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m1x8_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m2x2_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m2x3_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m2x4_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint8m4x2_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m1x2_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m1x3_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m1x4_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m1x5_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m1x6_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m1x7_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m1x8_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m2x2_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m2x3_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m2x4_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint16m4x2_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m1x2_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m1x3_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m1x4_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m1x5_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m1x6_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m1x7_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m1x8_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m2x2_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m2x3_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m2x4_t, 0)
+DEF_RVV_TH_UINT_TUPLE_OPS (vuint32m4x2_t, 0)
+
#undef DEF_RVV_I_OPS
#undef DEF_RVV_U_OPS
#undef DEF_RVV_F_OPS
@@ -1559,3 +1639,5 @@ DEF_RVV_X2_WU_OPS (vuint32m4_t, 0)
#undef DEF_RVV_XFQF_OPS
#undef DEF_RVV_X2_U_OPS
#undef DEF_RVV_X2_WU_OPS
+#undef DEF_RVV_TH_INT_TUPLE_OPS
+#undef DEF_RVV_TH_UINT_TUPLE_OPS
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index f652a125dc3..a8967fcafc6 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -52,6 +52,7 @@
#include "riscv-vector-builtins-shapes.h"
#include "riscv-vector-builtins-bases.h"
#include "sifive-vector-builtins-bases.h"
+#include "thead-vector-builtins-bases.h"
using namespace riscv_vector;
@@ -571,6 +572,25 @@ static const rvv_type_info xfqf_ops[] = {
#include "riscv-vector-builtins-types.def"
{NUM_VECTOR_TYPES, 0}};
+/* A list of Int Tuple types will be registered for intrinsic functions. */
+static const rvv_type_info th_tuple_int_ops[] = {
+#define DEF_RVV_TH_INT_TUPLE_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
+#define DEF_RVV_TH_UINT_TUPLE_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+ {NUM_VECTOR_TYPES, 0}};
+
+/* A list of Int Tuple types will be registered for intrinsic functions. */
+static const rvv_type_info th_tuple_sint_ops[] = {
+#define DEF_RVV_TH_INT_TUPLE_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+ {NUM_VECTOR_TYPES, 0}};
+
+/* A list of Int Tuple types will be registered for intrinsic functions. */
+static const rvv_type_info th_tuple_uint_ops[] = {
+#define DEF_RVV_TH_UINT_TUPLE_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+ {NUM_VECTOR_TYPES, 0}};
+
static CONSTEXPR const rvv_arg_type_info rvv_arg_type_info_end
= rvv_arg_type_info (NUM_BASE_TYPES);
@@ -3343,6 +3363,30 @@ static CONSTEXPR const rvv_op_info sf_vc_v_fvw_ops
rvv_arg_type_info (RVV_BASE_x2_vector), /* Return type */
sf_vc_fvw_args /* Args */};
+/* A static operand information for vector_type func (const scalar_type *)
+ * function registration. */
+static CONSTEXPR const rvv_op_info th_tuple_v_sint_scalar_const_ptr_ops
+ = {th_tuple_sint_ops, /* Types */
+ OP_TYPE_v, /* Suffix */
+ rvv_arg_type_info (RVV_BASE_vector),/* Return type */
+ scalar_const_ptr_args /* Args */};
+
+/* A static operand information for vector_type func (const scalar_type *)
+ * function registration. */
+static CONSTEXPR const rvv_op_info th_tuple_v_uint_scalar_const_ptr_ops
+ = {th_tuple_uint_ops, /* Types */
+ OP_TYPE_v, /* Suffix */
+ rvv_arg_type_info (RVV_BASE_vector),/* Return type */
+ scalar_const_ptr_args /* Args */};
+
+/* A static operand information for void func (scalar_type *, vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info th_tuple_v_int_scalar_ptr_ops
+ = {th_tuple_int_ops, /* Types */
+ OP_TYPE_v, /* Suffix */
+ rvv_arg_type_info (RVV_BASE_void), /* Return type */
+ scalar_ptr_args /* Args */};
+
/* A list of all RVV base function types. */
static CONSTEXPR const function_type_info function_types[] = {
#define DEF_RVV_TYPE_INDEX(
\
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 854daa96e73..05199e1c272 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -11,6 +11,7 @@ riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.cc
$(CONFIG_H) \
$(srcdir)/config/riscv/riscv-ftypes.def \
$(srcdir)/config/riscv/riscv-vector-builtins-types.def \
$(srcdir)/config/riscv/sifive-vector-builtins-functions.def \
+ $(srcdir)/config/riscv/thead-vector-builtins-functions.def \
$(srcdir)/config/riscv/riscv-modes.def \
$(srcdir)/config/riscv/riscv-cmo.def \
$(srcdir)/config/riscv/riscv-scalar-crypto.def
@@ -26,8 +27,10 @@ riscv-vector-builtins.o:
$(srcdir)/config/riscv/riscv-vector-builtins.cc \
$(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \
$(srcdir)/config/riscv/riscv-vector-builtins-bases.h \
$(srcdir)/config/riscv/sifive-vector-builtins-bases.h \
+ $(srcdir)/config/riscv/thead-vector-builtins-bases.h \
$(srcdir)/config/riscv/riscv-vector-builtins-types.def \
$(srcdir)/config/riscv/sifive-vector-builtins-functions.def \
+ $(srcdir)/config/riscv/thead-vector-builtins-functions.def \
$(RISCV_BUILTINS_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/riscv-vector-builtins.cc
@@ -39,6 +42,7 @@ riscv-vector-builtins-shapes.o: \
$(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \
$(srcdir)/config/riscv/riscv-vector-builtins-bases.h \
$(srcdir)/config/riscv/sifive-vector-builtins-bases.h \
+ $(srcdir)/config/riscv/thead-vector-builtins-bases.h \
$(RISCV_BUILTINS_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/riscv-vector-builtins-shapes.cc
@@ -69,6 +73,19 @@ sifive-vector-builtins-bases.o: \
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/sifive-vector-builtins-bases.cc
+thead-vector-builtins-bases.o: \
+ $(srcdir)/config/riscv/thead-vector-builtins-bases.cc \
+ $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(RTL_H) \
+ $(TM_P_H) memmodel.h insn-codes.h $(OPTABS_H) $(RECOG_H) \
+ $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) fold-const.h $(GIMPLE_H) \
+ gimple-iterator.h gimplify.h explow.h $(EMIT_RTL_H) tree-vector-builder.h \
+ rtx-vector-builder.h \
+ $(srcdir)/config/riscv/riscv-vector-builtins-shapes.h \
+ $(srcdir)/config/riscv/thead-vector-builtins-bases.h \
+ $(RISCV_BUILTINS_H)
+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+ $(srcdir)/config/riscv/thead-vector-builtins-bases.cc
+
riscv-sr.o: $(srcdir)/config/riscv/riscv-sr.cc $(CONFIG_H) \
$(SYSTEM_H) $(TM_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
@@ -178,6 +195,8 @@ $(srcdir)/config/riscv/riscv-vector-builtins.def:
riscv-vector-type-indexer.gen.
$(srcdir)/config/riscv/riscv-vector-builtins.h:
$(srcdir)/config/riscv/riscv-vector-builtins.def
$(srcdir)/config/riscv/sifive-vector-builtins-functions.def:
riscv-vector-type-indexer.gen.def
$(srcdir)/config/riscv/riscv-vector-builtins.h:
$(srcdir)/config/riscv/sifive-vector-builtins-functions.def
+$(srcdir)/config/riscv/thead-vector-builtins-functions.def:
riscv-vector-type-indexer.gen.def
+$(srcdir)/config/riscv/riscv-vector-builtins.h:
$(srcdir)/config/riscv/thead-vector-builtins-functions.def
riscv-vector-type-indexer.gen.def: s-riscv-vector-type-indexer.gen.defs ; @true
diff --git a/gcc/config/riscv/thead-vector-builtins-bases.cc
b/gcc/config/riscv/thead-vector-builtins-bases.cc
new file mode 100644
index 00000000000..d1afcf80307
--- /dev/null
+++ b/gcc/config/riscv/thead-vector-builtins-bases.cc
@@ -0,0 +1,138 @@
+/* Function_base implementation for RISC-V 'XTheadvector' Extension for GNU
compiler.
+ Copyright (C) 2025 Free Software Foundation, Inc.
+ Contributed by Alibaba Damo Academy Xuantie Team.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "rtl.h"
+#include "tm_p.h"
+#include "memmodel.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "recog.h"
+#include "expr.h"
+#include "basic-block.h"
+#include "function.h"
+#include "fold-const.h"
+#include "gimple.h"
+#include "gimple-iterator.h"
+#include "gimplify.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "tree-vector-builder.h"
+#include "rtx-vector-builder.h"
+#include "riscv-vector-builtins.h"
+#include "riscv-vector-builtins-shapes.h"
+#include "thead-vector-builtins-bases.h"
+#include "riscv-vector-builtins-bases.h"
+
+using namespace riscv_vector;
+
+namespace riscv_vector {
+
+/* Implements th.vlseg (b/h/w)[u].v codegen. */
+template <bool IS_SIGNED = false>
+class th_vlseg : public function_base {
+public:
+ unsigned int call_properties (const function_instance &) const override {
+ return CP_READ_MEMORY;
+ }
+
+ bool can_be_overloaded_p (enum predication_type_index pred) const override {
+ return pred != PRED_TYPE_none;
+ }
+
+ rtx expand (function_expander &e) const override {
+ gcc_assert (TARGET_XTHEADVECTOR);
+ unsigned sew = GET_MODE_BITSIZE (GET_MODE_INNER (e.vector_mode ()));
+ int UNSPEC;
+ switch (sew)
+ {
+ case 8:
+ UNSPEC = IS_SIGNED ? UNSPEC_TH_VLSEGB : UNSPEC_TH_VLSEGBU;
+ break;
+ case 16:
+ UNSPEC = IS_SIGNED ? UNSPEC_TH_VLSEGH : UNSPEC_TH_VLSEGHU;
+ break;
+ case 32:
+ UNSPEC = IS_SIGNED ? UNSPEC_TH_VLSEGW : UNSPEC_TH_VLSEGWU;
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ return e.use_exact_insn (
+ code_for_pred_th_unit_seg_load (UNSPEC, e.vector_mode ()));
+ }
+};
+
+/* Implements th.vsseg (b/h/w)[u].v codegen. */
+class th_vsseg : public function_base {
+public:
+ bool apply_tail_policy_p () const override { return false; }
+ bool apply_mask_policy_p () const override { return false; }
+
+ unsigned int call_properties (const function_instance &) const override {
+ return CP_WRITE_MEMORY;
+ }
+
+ bool can_be_overloaded_p (enum predication_type_index) const override {
+ return true;
+ }
+
+ rtx expand (function_expander &e) const override {
+ gcc_assert (TARGET_XTHEADVECTOR);
+ unsigned sew = GET_MODE_BITSIZE (GET_MODE_INNER (e.vector_mode ()));
+ int UNSPEC;
+ switch (sew)
+ {
+ case 8:
+ UNSPEC = UNSPEC_TH_VLSEGB;
+ break;
+ case 16:
+ UNSPEC = UNSPEC_TH_VLSEGH;
+ break;
+ case 32:
+ UNSPEC = UNSPEC_TH_VLSEGW;
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ return e.use_exact_insn (
+ code_for_pred_th_unit_seg_store (UNSPEC, e.vector_mode ()));
+ }
+};
+
+/* Xtheadvector */
+static CONSTEXPR const th_vlseg<true> th_vlseg_obj;
+static CONSTEXPR const th_vlseg<false> th_vlsegu_obj;
+static CONSTEXPR const th_vsseg th_vsseg_obj;
+
+/* Declare the function base NAME, pointing it to an instance
+ of class <NAME>_obj. */
+#define BASE(NAME) \
+ namespace bases { const function_base *const NAME = &NAME##_obj; }
+
+/* xtheadvector seg load store*/
+BASE (th_vlseg)
+BASE (th_vlsegu)
+BASE (th_vsseg)
+} // end namespace riscv_vector
diff --git a/gcc/config/riscv/thead-vector-builtins-bases.h
b/gcc/config/riscv/thead-vector-builtins-bases.h
new file mode 100644
index 00000000000..6614c177504
--- /dev/null
+++ b/gcc/config/riscv/thead-vector-builtins-bases.h
@@ -0,0 +1,36 @@
+/* Function_base implementation for RISC-V 'XTheadvector' Extension for GNU
compiler.
+ Copyright (C) 2025 Free Software Foundation, Inc.
+ Contributed by Alibaba Damo Academy Xuantie Team.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_THEAD_VECTOR_BUILTINS_BASES_H
+#define GCC_THEAD_VECTOR_BUILTINS_BASES_H
+
+namespace riscv_vector {
+
+
+namespace bases {
+/* Xtheadvector */
+extern const function_base *const th_vlseg;
+extern const function_base *const th_vlsegu;
+extern const function_base *const th_vsseg;
+}
+
+} // end namespace riscv_vector
+
+#endif
diff --git a/gcc/config/riscv/thead-vector-builtins-functions.def
b/gcc/config/riscv/thead-vector-builtins-functions.def
index fd3ba29bae9..01eedc1571c 100644
--- a/gcc/config/riscv/thead-vector-builtins-functions.def
+++ b/gcc/config/riscv/thead-vector-builtins-functions.def
@@ -34,6 +34,10 @@ DEF_RVV_FUNCTION (vsuxb, th_indexed_loadstore_width,
none_m_preds, all_v_scalar_
DEF_RVV_FUNCTION (vsuxh, th_indexed_loadstore_width, none_m_preds,
all_v_scalar_ptr_index_ops)
DEF_RVV_FUNCTION (vsuxw, th_indexed_loadstore_width, none_m_preds,
all_v_scalar_ptr_index_ops)
DEF_RVV_FUNCTION (vext_x_v, th_extract, none_preds, iu_x_s_u_ops)
+DEF_RVV_FUNCTION (th_vlseg, th_seg_loadstore, full_preds,
th_tuple_v_sint_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vlsegu, th_seg_loadstore, full_preds,
th_tuple_v_uint_scalar_const_ptr_ops)
+DEF_RVV_FUNCTION (th_vsseg, th_seg_loadstore, none_m_preds,
th_tuple_v_int_scalar_ptr_ops)
+
#undef REQUIRED_EXTENSIONS
#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md
index 5a02debdd20..007682c3af5 100644
--- a/gcc/config/riscv/thead-vector.md
+++ b/gcc/config/riscv/thead-vector.md
@@ -25,6 +25,13 @@ (define_c_enum "unspec" [
UNSPEC_TH_VSUXW
UNSPEC_TH_VWLDST
+
+ UNSPEC_TH_VLSEGB
+ UNSPEC_TH_VLSEGBU
+ UNSPEC_TH_VLSEGH
+ UNSPEC_TH_VLSEGHU
+ UNSPEC_TH_VLSEGW
+ UNSPEC_TH_VLSEGWU
])
(define_int_iterator UNSPEC_TH_VLMEM_OP [
@@ -45,6 +52,12 @@ (define_int_iterator UNSPEC_TH_VLXMEM_OP [
UNSPEC_TH_VLXW UNSPEC_TH_VLXWU
])
+(define_int_iterator UNSPEC_TH_VLSEGMEM_OP[
+ UNSPEC_TH_VLSEGB UNSPEC_TH_VLSEGBU
+ UNSPEC_TH_VLSEGH UNSPEC_TH_VLSEGHU
+ UNSPEC_TH_VLSEGW UNSPEC_TH_VLSEGWU
+])
+
(define_int_attr vlmem_op_attr [
(UNSPEC_TH_VLB "b") (UNSPEC_TH_VLBU "bu")
(UNSPEC_TH_VLH "h") (UNSPEC_TH_VLHU "hu")
@@ -58,6 +71,9 @@ (define_int_attr vlmem_op_attr [
(UNSPEC_TH_VSUXB "b")
(UNSPEC_TH_VSUXH "h")
(UNSPEC_TH_VSUXW "w")
+ (UNSPEC_TH_VLSEGB "b") (UNSPEC_TH_VLSEGBU "bu")
+ (UNSPEC_TH_VLSEGH "h") (UNSPEC_TH_VLSEGHU "hu")
+ (UNSPEC_TH_VLSEGW "w") (UNSPEC_TH_VLSEGWU "wu")
])
(define_int_attr vlmem_order_attr [
@@ -90,9 +106,89 @@ (define_int_iterator UNSPEC_TH_VSXMEM_OP [
UNSPEC_TH_VSUXW
])
+(define_int_iterator UNSPEC_TH_VSSEGMEM_OP[
+ UNSPEC_TH_VLSEGB
+ UNSPEC_TH_VLSEGH
+ UNSPEC_TH_VLSEGW
+])
+
(define_mode_iterator V_VLS_VT [V VLS VT])
(define_mode_iterator V_VB_VLS_VT [V VB VLS VT])
+(define_mode_attr th_width[
+ (RVVM8QI "b") (RVVM4QI "b") (RVVM2QI "b") (RVVM1QI "b") (RVVMF2QI "b")
(RVVMF4QI "b") (RVVMF8QI "b")
+
+ (RVVM8HI "h") (RVVM4HI "h") (RVVM2HI "h") (RVVM1HI "h") (RVVMF2HI "h")
(RVVMF4HI "h")
+
+ (RVVM8BF "h") (RVVM4BF "h") (RVVM2BF "h") (RVVM1BF "h") (RVVMF2BF "h")
(RVVMF4BF "h")
+
+ (RVVM8HF "h") (RVVM4HF "h") (RVVM2HF "h") (RVVM1HF "h") (RVVMF2HF "h")
(RVVMF4HF "h")
+
+ (RVVM8SI "w") (RVVM4SI "w") (RVVM2SI "w") (RVVM1SI "w") (RVVMF2SI "w")
+
+ (RVVM8SF "w") (RVVM4SF "w") (RVVM2SF "w") (RVVM1SF "w") (RVVMF2SF "w")
+
+ (RVVM1x8QI "b") (RVVMF2x8QI "b") (RVVMF4x8QI "b") (RVVMF8x8QI "b")
+ (RVVM1x7QI "b") (RVVMF2x7QI "b") (RVVMF4x7QI "b") (RVVMF8x7QI "b")
+ (RVVM1x6QI "b") (RVVMF2x6QI "b") (RVVMF4x6QI "b") (RVVMF8x6QI "b")
+ (RVVM1x5QI "b") (RVVMF2x5QI "b") (RVVMF4x5QI "b") (RVVMF8x5QI "b")
+ (RVVM2x4QI "b") (RVVM1x4QI "b") (RVVMF2x4QI "b") (RVVMF4x4QI "b")
(RVVMF8x4QI "b")
+ (RVVM2x3QI "b") (RVVM1x3QI "b") (RVVMF2x3QI "b") (RVVMF4x3QI "b")
(RVVMF8x3QI "b")
+ (RVVM4x2QI "b") (RVVM2x2QI "b") (RVVM1x2QI "b") (RVVMF2x2QI "b") (RVVMF4x2QI
"b") (RVVMF8x2QI "b")
+
+ (RVVM1x8HI "h") (RVVMF2x8HI "h") (RVVMF4x8HI "h")
+ (RVVM1x7HI "h") (RVVMF2x7HI "h") (RVVMF4x7HI "h")
+ (RVVM1x6HI "h") (RVVMF2x6HI "h") (RVVMF4x6HI "h")
+ (RVVM1x5HI "h") (RVVMF2x5HI "h") (RVVMF4x5HI "h")
+ (RVVM2x4HI "h") (RVVM1x4HI "h") (RVVMF2x4HI "h") (RVVMF4x4HI "h")
+ (RVVM2x3HI "h") (RVVM1x3HI "h") (RVVMF2x3HI "h") (RVVMF4x3HI "h")
+ (RVVM4x2HI "h") (RVVM2x2HI "h") (RVVM1x2HI "h") (RVVMF2x2HI "h") (RVVMF4x2HI
"h")
+
+ (RVVM1x8BF "h") (RVVMF2x8BF "h") (RVVMF4x8BF "h")
+ (RVVM1x7BF "h") (RVVMF2x7BF "h") (RVVMF4x7BF "h")
+ (RVVM1x6BF "h") (RVVMF2x6BF "h") (RVVMF4x6BF "h")
+ (RVVM1x5BF "h") (RVVMF2x5BF "h") (RVVMF4x5BF "h")
+ (RVVM2x4BF "h") (RVVM1x4BF "h") (RVVMF2x4BF "h") (RVVMF4x4BF "h")
+ (RVVM2x3BF "h") (RVVM1x3BF "h") (RVVMF2x3BF "h") (RVVMF4x3BF "h")
+ (RVVM4x2BF "h") (RVVM2x2BF "h") (RVVM1x2BF "h") (RVVMF2x2BF "h") (RVVMF4x2BF
"h")
+
+ (RVVM1x8HF "h") (RVVMF2x8HF "h") (RVVMF4x8HF "h")
+ (RVVM1x7HF "h") (RVVMF2x7HF "h") (RVVMF4x7HF "h")
+ (RVVM1x6HF "h") (RVVMF2x6HF "h") (RVVMF4x6HF "h")
+ (RVVM1x5HF "h") (RVVMF2x5HF "h") (RVVMF4x5HF "h")
+ (RVVM2x4HF "h") (RVVM1x4HF "h") (RVVMF2x4HF "h") (RVVMF4x4HF "h")
+ (RVVM2x3HF "h") (RVVM1x3HF "h") (RVVMF2x3HF "h") (RVVMF4x3HF "h")
+ (RVVM4x2HF "h") (RVVM2x2HF "h") (RVVM1x2HF "h") (RVVMF2x2HF "h") (RVVMF4x2HF
"h")
+
+ (RVVM1x8SI "w") (RVVMF2x8SI "w")
+ (RVVM1x7SI "w") (RVVMF2x7SI "w")
+ (RVVM1x6SI "w") (RVVMF2x6SI "w")
+ (RVVM1x5SI "w") (RVVMF2x5SI "w")
+ (RVVM2x4SI "w") (RVVM1x4SI "w") (RVVMF2x4SI "w")
+ (RVVM2x3SI "w") (RVVM1x3SI "w") (RVVMF2x3SI "w")
+ (RVVM4x2SI "w") (RVVM2x2SI "w") (RVVM1x2SI "w") (RVVMF2x2SI "w")
+
+ (RVVM1x8SF "w") (RVVMF2x8SF "w")
+ (RVVM1x7SF "w") (RVVMF2x7SF "w")
+ (RVVM1x6SF "w") (RVVMF2x6SF "w")
+ (RVVM1x5SF "w") (RVVMF2x5SF "w")
+ (RVVM2x4SF "w") (RVVM1x4SF "w") (RVVMF2x4SF "w")
+ (RVVM2x3SF "w") (RVVM1x3SF "w") (RVVMF2x3SF "w")
+ (RVVM4x2SF "w") (RVVM2x2SF "w") (RVVM1x2SF "w") (RVVMF2x2SF "w")
+
+ ;; VLS modes.
+ (V1QI "b") (V2QI "b") (V4QI "b") (V8QI "b") (V16QI "b") (V32QI "b") (V64QI
"b") (V128QI "b") (V256QI "b") (V512QI "b")
+ (V1024QI "b") (V2048QI "b") (V4096QI "b")
+ (V1HI "h") (V2HI "h") (V4HI "h") (V8HI "h") (V16HI "h") (V32HI "h") (V64HI
"h") (V128HI "h") (V256HI "h")
+ (V512HI "h") (V1024HI "h") (V2048HI "h")
+ (V1SI "w") (V2SI "w") (V4SI "w") (V8SI "w") (V16SI "w") (V32SI "w") (V64SI
"w") (V128SI "w") (V256SI "w")
+ (V512SI "w") (V1024SI "w")
+ (V1HF "h") (V2HF "h") (V4HF "h") (V8HF "h") (V16HF "h") (V32HF "h") (V64HF
"h") (V128HF "h") (V256HF "h")
+ (V512HF "h") (V1024HF "h") (V2048HF "h")
+ (V1SF "w") (V2SF "w") (V4SF "w") (V8SF "w") (V16SF "w") (V32SF "w") (V64SF
"w") (V128SF "w") (V256SF "w")
+ (V512SF "w") (V1024SF "w")
+])
+
(define_split
[(set (match_operand:V_VB_VLS_VT 0 "reg_or_mem_operand")
(match_operand:V_VB_VLS_VT 1 "reg_or_mem_operand"))]
@@ -350,3 +446,40 @@ (define_insn "*pred_th_extract<mode>"
"vext.x.v\t%0,%1,%2"
[(set_attr "type" "vimovvx")
(set_attr "mode" "<MODE>")])
+
+(define_insn "@pred_th_unit_seg_load<vlmem_op_attr><mode>"
+ [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
+ (if_then_else:VT
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VLSEGMEM_OP)
+ (unspec:VT
+ [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
+ (mem:BLK (scratch))] UNSPEC_TH_VLSEGMEM_OP)
+ (match_operand:VT 2 "vector_merge_operand" " 0, vu,
vu")))]
+ "TARGET_XTHEADVECTOR"
+ "vlseg<nf><vlmem_op_attr>.v\t%0,(%z3)%p1"
+ [(set_attr "type" "vlsegde")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "@pred_th_unit_seg_store<vlmem_op_attr><mode>"
+ [(set (mem:BLK (scratch))
+ (unspec:BLK
+ [(unspec:<VM>
+ [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
+ (match_operand 3 "vector_length_operand" " rK")
+ (match_operand 4 "const_int_operand" " i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_TH_VSSEGMEM_OP)
+ (match_operand 1 "pmode_reg_or_0_operand" " rJ")
+ (match_operand:VT 2 "register_operand" " vr")
+ (mem:BLK (scratch))] UNSPEC_TH_VSSEGMEM_OP))]
+ "TARGET_XTHEADVECTOR"
+ "vsseg<nf><vlmem_op_attr>.v\t%2,(%z1)%p0"
+ [(set_attr "type" "vssegte")
+ (set_attr "mode" "<MODE>")])
diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index de23e410d4c..b78e2762cfa 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -1059,12 +1059,17 @@ th_asm_output_opcode (FILE *asm_out_file, const char *p)
get_attr_type (current_output_insn) == TYPE_VSSEGTE
? fputs ("th.vsseg", asm_out_file)
: fputs ("th.vlseg", asm_out_file);
- asm_fprintf (asm_out_file, "%c", p[5]);
- fputs ("e", asm_out_file);
- if (strstr (p, "e8"))
- return p+8;
- else
- return p+9;
+ if (strstr (p, "b") || strstr (p, "h") || strstr (p, "w"))
+ return p+5;
+ else
+ {
+ asm_fprintf (asm_out_file, "%c", p[5]);
+ fputs ("e", asm_out_file);
+ if (strstr (p, "e8"))
+ return p+8;
+ else
+ return p+9;
+ }
}
if (get_attr_type (current_output_insn) == TYPE_VLSEGDS ||
@@ -1073,36 +1078,51 @@ th_asm_output_opcode (FILE *asm_out_file, const char *p)
get_attr_type (current_output_insn) == TYPE_VSSEGTS
? fputs ("th.vssseg", asm_out_file)
: fputs ("th.vlsseg", asm_out_file);
- asm_fprintf (asm_out_file, "%c", p[6]);
- fputs ("e", asm_out_file);
- if (strstr (p, "e8"))
- return p+9;
- else
- return p+10;
+ if (strstr (p, "b") || strstr (p, "h") || strstr (p, "w"))
+ return p+6;
+ else
+ {
+ asm_fprintf (asm_out_file, "%c", p[6]);
+ fputs ("e", asm_out_file);
+ if (strstr (p, "e8"))
+ return p+9;
+ else
+ return p+10;
+ }
}
if (get_attr_type (current_output_insn) == TYPE_VLSEGDUX ||
get_attr_type (current_output_insn) == TYPE_VLSEGDOX)
{
fputs ("th.vlxseg", asm_out_file);
- asm_fprintf (asm_out_file, "%c", p[7]);
- fputs ("e", asm_out_file);
- if (strstr (p, "ei8"))
- return p+11;
- else
- return p+12;
+ if (strstr (p, "b") || strstr (p, "h") || strstr (p, "w"))
+ return p+6;
+ else
+ {
+ asm_fprintf (asm_out_file, "%c", p[7]);
+ fputs ("e", asm_out_file);
+ if (strstr (p, "ei8"))
+ return p+11;
+ else
+ return p+12;
+ }
}
if (get_attr_type (current_output_insn) == TYPE_VSSEGTUX ||
get_attr_type (current_output_insn) == TYPE_VSSEGTOX)
{
fputs ("th.vsxseg", asm_out_file);
- asm_fprintf (asm_out_file, "%c", p[7]);
- fputs ("e", asm_out_file);
- if (strstr (p, "ei8"))
- return p+11;
- else
- return p+12;
+ if (strstr (p, "b") || strstr (p, "h") || strstr (p, "w"))
+ return p+6;
+ else
+ {
+ asm_fprintf (asm_out_file, "%c", p[7]);
+ fputs ("e", asm_out_file);
+ if (strstr (p, "ei8"))
+ return p+11;
+ else
+ return p+12;
+ }
}
if (get_attr_type (current_output_insn) == TYPE_VNSHIFT)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlseg-vsseg.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlseg-vsseg.c
new file mode 100644
index 00000000000..1911824bbfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlseg-vsseg.c
@@ -0,0 +1,118 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" { target rv32 } }
*/
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** li\s+[a-x0-9]+,4
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vlseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** th\.vlseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vsseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** ret
+*/
+void f1 (void * in, void *out)
+{
+ vint16m1x2_t v = __riscv_th_vlseg2h_v_i16m1x2 (in, 4);
+ vint16m1x2_t v2 = __riscv_th_vlseg2h_v_i16m1x2_tu (v, in, 4);
+ vint16m1_t v2_0 = __riscv_vget_i16m1 (v2, 0);
+ vint16m1_t v2_1 = __riscv_vget_i16m1 (v2, 1);
+ vint16m1_t v3_0 = __riscv_vadd_vv_i16m1 (v2_0, v2_0, 4);
+ vint16m1_t v3_1 = __riscv_vadd_vv_i16m1 (v2_1, v2_1, 4);
+ vint16m1_t v4_0 = __riscv_vadd_vv_i16m1 (v3_0, v2_0, 4);
+ vint16m1_t v4_1 = __riscv_vadd_vv_i16m1 (v3_1, v2_1, 4);
+ vint16m1x2_t v4 = __riscv_vset (v4, 0, v4_0);
+ v4 = __riscv_vset (v4, 1, v4_1);
+ __riscv_th_vsseg2h_v_i16m1x2 (out, v4, 4);
+}
+
+/*
+** f2:
+** li\s+[a-x0-9]+,4
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vlseg2h\.v\s+v[0-9]+,\([a-x0-9]+\),v0\.t
+** th\.vlseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vsseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** ret
+*/
+void f2 (void * in, void *out, vbool16_t mask)
+{
+ vint16m1x2_t v = __riscv_th_vlseg2h_v_i16m1x2 (in, 4);
+ vint16m1x2_t v2 = __riscv_th_vlseg2h_v_i16m1x2_m (mask, in, 4);
+ vint16m1_t v_0 = __riscv_vget_i16m1(v, 0);
+ vint16m1_t v_1 = __riscv_vget_i16m1(v, 1);
+ vint16m1_t v2_0 = __riscv_vget_i16m1 (v2, 0);
+ vint16m1_t v2_1 = __riscv_vget_i16m1 (v2, 1);
+ vint16m1_t v3_0 = __riscv_vadd_vv_i16m1 (v_0, v2_0, 4);
+ vint16m1_t v3_1 = __riscv_vadd_vv_i16m1 (v_1, v2_1, 4);
+ vint16m1_t v4_0 = __riscv_vadd_vv_i16m1 (v3_0, v2_0, 4);
+ vint16m1_t v4_1 = __riscv_vadd_vv_i16m1 (v3_1, v2_1, 4);
+ vint16m1x2_t v4 = __riscv_vset (v4, 0, v4_0);
+ v4 = __riscv_vset (v4, 1, v4_1);
+ __riscv_th_vsseg2h_v_i16m1x2 (out, v4, 4);
+}
+
+/*
+** f3:
+** li\s+[a-x0-9]+,4
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vlseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** th\.vsetvli\s+[a-x0-9]+,zero,e16,m1
+** th\.vmv\.v\.i\s+v[0-9]+,0
+** th\.vmv\.v\.i\s+v[0-9]+,0
+** th\.vmv\.v\.i\s+v[0-9]+,0
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vlseg2h\.v\s+v[0-9]+,\([a-x0-9]+\),v0\.t
+** th\.vsetvli\s+[a-x0-9]+,zero,e16,m1
+** th\.vmv\.v\.i\s+v[0-9]+,0
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0\.t
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0\.t
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0\.t
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0\.t
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vsseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** ret
+*/
+void f3 (void * in, void *out, vbool16_t mask)
+{
+ vint16m1x2_t v = __riscv_th_vlseg2h_v_i16m1x2 (in, 4);
+ vint16m1x2_t v2 = __riscv_th_vlseg2h_v_i16m1x2_tumu (mask, v, in, 4);
+ vint16m1_t v2_0 = __riscv_vget_i16m1 (v2, 0);
+ vint16m1_t v2_1 = __riscv_vget_i16m1 (v2, 1);
+ vint16m1_t v3_0 = __riscv_vadd_vv_i16m1_tumu (mask, v3_0, v2_0, v2_0, 4);
+ vint16m1_t v3_1 = __riscv_vadd_vv_i16m1_tumu (mask, v3_1, v2_1, v2_1, 4);
+ vint16m1_t v4_0 = __riscv_vadd_vv_i16m1_tumu (mask, v4_0, v3_0, v2_0, 4);
+ vint16m1_t v4_1 = __riscv_vadd_vv_i16m1_tumu (mask, v4_1, v3_1, v2_1, 4);
+ vint16m1x2_t v4 = __riscv_vset (v4, 0, v4_0);
+ v4 = __riscv_vset (v4, 1, v4_1);
+ __riscv_th_vsseg2h_v_i16m1x2 (out, v4, 4);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlsegu-vsseg.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlsegu-vsseg.c
new file mode 100644
index 00000000000..c3791f7872f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlsegu-vsseg.c
@@ -0,0 +1,116 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcxtheadvector -mabi=ilp32d -O3" { target rv32 } }
+ */
+/* { dg-final { check-function-bodies "**" "" } } */
+#include "riscv_th_vector.h"
+
+/*
+** f1:
+** li\s+[a-x0-9]+,4
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vlseg2hu\.v\s+v[0-9]+,\([a-x0-9]+\)
+** th\.vlseg2hu\.v\s+v[0-9]+,\([a-x0-9]+\)
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vsseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** ret
+*/
+void f1(void *in, void *out) {
+ vuint16m1x2_t v = __riscv_th_vlseg2hu_v_u16m1x2(in, 4);
+ vuint16m1x2_t v2 = __riscv_th_vlseg2hu_v_u16m1x2_tu(v, in, 4);
+ vuint16m1_t v2_0 = __riscv_vget_u16m1(v2, 0);
+ vuint16m1_t v2_1 = __riscv_vget_u16m1(v2, 1);
+ vuint16m1_t v3_0 = __riscv_vadd_vv_u16m1(v2_0, v2_0, 4);
+ vuint16m1_t v3_1 = __riscv_vadd_vv_u16m1(v2_1, v2_1, 4);
+ vuint16m1_t v4_0 = __riscv_vadd_vv_u16m1(v3_0, v2_0, 4);
+ vuint16m1_t v4_1 = __riscv_vadd_vv_u16m1(v3_1, v2_1, 4);
+ vuint16m1x2_t v4 = __riscv_vset(v4, 0, v4_0);
+ v4 = __riscv_vset(v4, 1, v4_1);
+ __riscv_th_vsseg2h_v_u16m1x2(out, v4, 4);
+}
+
+/*
+** f2:
+** li\s+[a-x0-9]+,4
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vlseg2hu\.v\s+v[0-9]+,\([a-x0-9]+\),v0\.t
+** th\.vlseg2hu\.v\s+v[0-9]+,\([a-x0-9]+\)
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vsseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** ret
+*/
+void f2(void *in, void *out, vbool16_t mask) {
+ vuint16m1x2_t v = __riscv_th_vlseg2hu_v_u16m1x2(in, 4);
+ vuint16m1x2_t v2 = __riscv_th_vlseg2hu_v_u16m1x2_m(mask, in, 4);
+ vuint16m1_t v_0 = __riscv_vget_u16m1(v, 0);
+ vuint16m1_t v_1 = __riscv_vget_u16m1(v, 1);
+ vuint16m1_t v2_0 = __riscv_vget_u16m1(v2, 0);
+ vuint16m1_t v2_1 = __riscv_vget_u16m1(v2, 1);
+ vuint16m1_t v3_0 = __riscv_vadd_vv_u16m1(v_0, v2_0, 4);
+ vuint16m1_t v3_1 = __riscv_vadd_vv_u16m1(v_1, v2_1, 4);
+ vuint16m1_t v4_0 = __riscv_vadd_vv_u16m1(v3_0, v2_0, 4);
+ vuint16m1_t v4_1 = __riscv_vadd_vv_u16m1(v3_1, v2_1, 4);
+ vuint16m1x2_t v4 = __riscv_vset(v4, 0, v4_0);
+ v4 = __riscv_vset(v4, 1, v4_1);
+ __riscv_th_vsseg2h_v_u16m1x2(out, v4, 4);
+}
+
+/*
+** f3:
+** li\s+[a-x0-9]+,4
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vlseg2hu\.v\s+v[0-9]+,\([a-x0-9]+\)
+** th\.vsetvli\s+[a-x0-9]+,zero,e16,m1
+** th\.vmv\.v\.i\s+v[0-9]+,0
+** th\.vmv\.v\.i\s+v[0-9]+,0
+** th\.vmv\.v\.i\s+v[0-9]+,0
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vlseg2hu\.v\s+v[0-9]+,\([a-x0-9]+\),v0\.t
+** th\.vsetvli\s+[a-x0-9]+,zero,e16,m1
+** th\.vmv\.v\.i\s+v[0-9]+,0
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0\.t
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0\.t
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0\.t
+** th\.vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0\.t
+** th\.vsetvli\s+zero,zero,e16,m1
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vmv\.v\.v\s+v[0-9]+,v[0-9]+
+** th\.vsetvli\s+zero,[a-x0-9]+,e16,m1
+** th\.vsseg2h\.v\s+v[0-9]+,\([a-x0-9]+\)
+** ret
+*/
+void f3(void *in, void *out, vbool16_t mask) {
+ vuint16m1x2_t v = __riscv_th_vlseg2hu_v_u16m1x2(in, 4);
+ vuint16m1x2_t v2 = __riscv_th_vlseg2hu_v_u16m1x2_tumu(mask, v, in, 4);
+ vuint16m1_t v2_0 = __riscv_vget_u16m1(v2, 0);
+ vuint16m1_t v2_1 = __riscv_vget_u16m1(v2, 1);
+ vuint16m1_t v3_0 = __riscv_vadd_vv_u16m1_tumu(mask, v3_0, v2_0, v2_0, 4);
+ vuint16m1_t v3_1 = __riscv_vadd_vv_u16m1_tumu(mask, v3_1, v2_1, v2_1, 4);
+ vuint16m1_t v4_0 = __riscv_vadd_vv_u16m1_tumu(mask, v4_0, v3_0, v2_0, 4);
+ vuint16m1_t v4_1 = __riscv_vadd_vv_u16m1_tumu(mask, v4_1, v3_1, v2_1, 4);
+ vuint16m1x2_t v4 = __riscv_vset(v4, 0, v4_0);
+ v4 = __riscv_vset(v4, 1, v4_1);
+ __riscv_th_vsseg2h_v_u16m1x2(out, v4, 4);
+}
--
2.47.1
