On 6/6/25 11:58 AM, Robin Dapp wrote:
Note it’s far from obvious to me whether for stride and gather loads
the alignment of the elements loaded falls under the scalar or vector
load restriction. Is this explicitly spelled out for risc-v or is
that your interpretation?
We have the following in the vector spec:
If an element accessed by a vector memory instruction is not naturally
aligned to the size of the element, either the element is transferred
successfully or an address misaligned exception is raised on that
element.
And, at least on our uarch, they are distinct from scalar accesses. So
it's not like we perform scalar loads under the hood and then transfer
them to the vector unit.
Right. The spec allows different behavior between scalar and vector WRT
alignments. We see that showing in up designs too -- the BPI F3 for
example has differing behavior for unaligned scalar and vector loads.
jeff
