Re: [PATCH 4/7 v2] RISC-V: Add support for the XAndesvbfhcvt ISA extension.

[KuanLin Chen]

Hi Kito,

Kito Cheng <kito.ch...@gmail.com> 於 2025年7月30日 週三 上午9:01寫道：
>
> > +(define_insn "@nds_vfwcvt_bf16<mode>"
> > +  [(set (match_operand:NDS_VWEXTBF 0 "register_operand"                  
> > "=&vr")
> > +       (unspec_volatile:NDS_VWEXTBF
> > +         [(float_extend:NDS_VWEXTBF
> > +            (match_operand:<NDS_V_DOUBLE_TRUNC_BF> 1 "register_operand" "  
> > vr"))]
> > +          UNSPEC_NDS_VFWCVTBF16))]
> > +  "TARGET_VECTOR && TARGET_XANDESVBFHCVT"
> > +  "nds.vfwcvt.s.bf16\t%0,%1"
> > +  [(set_attr "type" "fcvt")
> > +   (set_attr "mode" "<NDS_V_DOUBLE_TRUNC_BF>")])
> > +
> > +(define_insn "@nds_vfncvt_bf16<mode>"
> > +  [(set (match_operand:<NDS_V_DOUBLE_TRUNC_BF> 0 "register_operand"   
> > "=&vr")
> > +       (unspec_volatile:<NDS_V_DOUBLE_TRUNC_BF>
> > +         [(float_truncate:<NDS_V_DOUBLE_TRUNC_BF>
> > +            (match_operand:NDS_VWEXTBF 1 "register_operand"          "  
> > vr"))]
> > +          UNSPEC_NDS_VFNCVTBF16))]
> > +  "TARGET_VECTOR && TARGET_XANDESVBFHCVT"
> > +  "nds.vfncvt.bf16.s\t%0,%1"
> > +  [(set_attr "type" "fcvt")
> > +   (set_attr "mode" "<NDS_V_DOUBLE_TRUNC_BF>")])
>
> Where are VL and VTYPE operands? I am not sure why this can work
> correctly with vsetvli pass?
> and what's different between vfncvtbf16.f.f.w and vfwcvtbf16.f.f.v?
> I assume that pattern should at least add use (reg:SI VTYPE_REGNUM)
> like @pred_trunc<mode>_to_bf16 and @pred_extend_bf16_to_<mode>?


These two patterns are old design which Andes released to customers in 2023.
They don't depend on vsetvli pass. Users must specify vsetvl explicitly.
And we plan to deprecate these patterns in two years.
Thanks for your review.