From: Pan Li <pan2...@intel.com>
Add asm dump check and run test for vec_duplicate + vmacc.vvm
combine to vmacc.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
for vx combine.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 3 +++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 3 +++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 3 +++
.../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 3 +++
.../riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c | 16 ++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c | 16 ++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c | 16 ++++++++++++++++
.../riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c | 16 ++++++++++++++++
16 files changed, 100 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index cb62e0f9619..187b681bea2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint16_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index e2a5dbbc859..a3a785abf06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint32_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 8e7a7889261..4142e1b67ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint64_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -23,3 +25,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
"-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
} } } } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index d213c18d9ae..5b36f084ac8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint8_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vaaddu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 365e650ef12..9c034dcf7c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint16_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vsaddu.vx} } } */
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index c8fd42a52c4..ce50de69190 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint32_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vsaddu.vx} } } */
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index bdb76b471c0..5cd6b417092 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint64_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vsaddu.vx} } } */
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index fc9c10125a8..f9d4a63198d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint8_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vsaddu.vx} } } */
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 121daebcf55..2264014e2e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint16_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vsaddu.vx} } } */
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 9616e7f2fe4..928909386d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint32_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vsaddu.vx} } } */
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index cf985f0ba26..271b4d62e3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint64_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vsaddu.vx} } } */
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 3bb382dd395..f75695b6b5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -2,10 +2,12 @@
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */
#include "vx_binary.h"
+#include "vx_ternary.h"
#define T uint8_t
TEST_BINARY_VX_UNSIGNED_0(T)
+TEST_TERNARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -20,3 +22,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
/* { dg-final { scan-assembler-not {vsaddu.vx} } } */
/* { dg-final { scan-assembler-not {vssubu.vx} } } */
/* { dg-final { scan-assembler-not {vaaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vmacc.vx} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c
new file mode 100644
index 00000000000..8ec9d05b0b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T uint16_t
+#define NAME macc
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c
new file mode 100644
index 00000000000..46d5c4d3416
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T uint32_t
+#define NAME macc
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c
new file mode 100644
index 00000000000..cd857b6b6b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T uint64_t
+#define NAME macc
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c
new file mode 100644
index 00000000000..05fa397df38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmacc-run-1-u8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T uint8_t
+#define NAME macc
+#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+ RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"
--
2.43.0
