On Thu, Sep 25, 2025 at 08:02:48PM -0700, Kees Cook wrote:
> Assembly Code Pattern for ARM 32-bit:
> push {r0, r1} ; Spill r0, r1
> ldr r0, [target, #-4] ; Load actual type ID from preamble
> movw r1, #type_id_low ; Load expected type (lower 16 bits)
> movt r1, #type_id_high ; Load upper 16 bits with top instruction
> cmp r0, r1 ; Compare type IDs directly
> pop [r0, r1] ; Reload r0, r1
> beq .Lkcfi_call ; Branch if typeids match
> .Lkcfi_trap: udf #udf_value ; Undefined instruction trap with encoding
> .Lkcfi_call: blx/bx target ; Execute validated indirect transfer
Agh, I missed changing this part of the commit log to reflect the new
eor sequence. I'll get that fixed.
--
Kees Cook
