The target does not seem to have a maintainer listed, I've CC'ed a group of
global maintainers instead hoping one of you could approve it.
This patch is a mechanical rewrite of the widen_[us]sum optabs from a direct to
a conversion optab. The result of which requires the output mode to be added to
the existing patterns.
No change in functionality is expected.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
PR middle-end/122069
* config/ia64/vect.md (widen_usumv8qi3): Renamed ...
(widen_usumv4hiv8qi3): ... into this.
(widen_usumv4hi3): Renamed ...
(widen_usumv2siv4hi3): ... into this.
(widen_ssumv8qi3): Renamed ...
(widen_ssumv4hiv8qi3): ... into this.
(widen_ssumv4hi3): Renamed ...
(widen_ssumv2siv4hi3): ... into this.
---
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index
f17c51496bc54e387487f147e81b9d1d3ebffe34..9d9df1d5e8288a859ccc7a9dec4fc97fb417afcf
100644
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -584,7 +584,7 @@ (define_expand "vec_shr_<mode>"
operands[1] = gen_lowpart (DImode, operands[1]);
})
-(define_expand "widen_usumv8qi3"
+(define_expand "widen_usumv4hiv8qi3"
[(match_operand:V4HI 0 "gr_register_operand" "")
(match_operand:V8QI 1 "gr_register_operand" "")
(match_operand:V4HI 2 "gr_register_operand" "")]
@@ -594,7 +594,7 @@ (define_expand "widen_usumv8qi3"
DONE;
})
-(define_expand "widen_usumv4hi3"
+(define_expand "widen_usumv2siv4hi3"
[(match_operand:V2SI 0 "gr_register_operand" "")
(match_operand:V4HI 1 "gr_register_operand" "")
(match_operand:V2SI 2 "gr_register_operand" "")]
@@ -604,7 +604,7 @@ (define_expand "widen_usumv4hi3"
DONE;
})
-(define_expand "widen_ssumv8qi3"
+(define_expand "widen_ssumv4hiv8qi3"
[(match_operand:V4HI 0 "gr_register_operand" "")
(match_operand:V8QI 1 "gr_register_operand" "")
(match_operand:V4HI 2 "gr_register_operand" "")]
@@ -614,7 +614,7 @@ (define_expand "widen_ssumv8qi3"
DONE;
})
-(define_expand "widen_ssumv4hi3"
+(define_expand "widen_ssumv2siv4hi3"
[(match_operand:V2SI 0 "gr_register_operand" "")
(match_operand:V4HI 1 "gr_register_operand" "")
(match_operand:V2SI 2 "gr_register_operand" "")]
--
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index f17c51496bc54e387487f147e81b9d1d3ebffe34..9d9df1d5e8288a859ccc7a9dec4fc97fb417afcf 100644
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -584,7 +584,7 @@ (define_expand "vec_shr_<mode>"
operands[1] = gen_lowpart (DImode, operands[1]);
})
-(define_expand "widen_usumv8qi3"
+(define_expand "widen_usumv4hiv8qi3"
[(match_operand:V4HI 0 "gr_register_operand" "")
(match_operand:V8QI 1 "gr_register_operand" "")
(match_operand:V4HI 2 "gr_register_operand" "")]
@@ -594,7 +594,7 @@ (define_expand "widen_usumv8qi3"
DONE;
})
-(define_expand "widen_usumv4hi3"
+(define_expand "widen_usumv2siv4hi3"
[(match_operand:V2SI 0 "gr_register_operand" "")
(match_operand:V4HI 1 "gr_register_operand" "")
(match_operand:V2SI 2 "gr_register_operand" "")]
@@ -604,7 +604,7 @@ (define_expand "widen_usumv4hi3"
DONE;
})
-(define_expand "widen_ssumv8qi3"
+(define_expand "widen_ssumv4hiv8qi3"
[(match_operand:V4HI 0 "gr_register_operand" "")
(match_operand:V8QI 1 "gr_register_operand" "")
(match_operand:V4HI 2 "gr_register_operand" "")]
@@ -614,7 +614,7 @@ (define_expand "widen_ssumv8qi3"
DONE;
})
-(define_expand "widen_ssumv4hi3"
+(define_expand "widen_ssumv2siv4hi3"
[(match_operand:V2SI 0 "gr_register_operand" "")
(match_operand:V4HI 1 "gr_register_operand" "")
(match_operand:V2SI 2 "gr_register_operand" "")]
