在 2025/11/17 上午12:52, Xi Ruoyao 写道:
On Fri, 2025-11-14 at 10:59 +0800, zhaozhou wrote:
In some cases, the pre pass will separate the shift and add of
shift+add+ld/st ins into different blocks, resulting in combine
ldx/stx
instead of alsl, but for consecutive reg+reg memory access
instructions,
this may cause read port conflicts and reduce efficiency.
Try to directly generate alsl, processing the following RTL into alsl:
(plus:DI (mult:DI (reg/v:DI 81 [ index ])
(const_int 4 [0x4]))
(reg/f:DI 84))
todo:
(plus:DI (ashift:DI (reg/v:DI 81 [ index ])
(const_int 2 [0x4]))
(reg/f:DI 84))
ADD_OPTIONS: -mcombine-addr-alsl
gcc/config/loongarch/loongarch.opt.urls needs to be regenerated.
Thank you for your reminder. I will update
gcc/config/loongarch/loongarch.opt.urls
and send Patch v2.
And why not just make this the default?
This is my thinks: First, this patch will prevent the generation of
mem-related ldx/stx
instructions, and do this not necessary for us in all cases.
Second, as for testcase
gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c,
if patch is enabled by default, the testcase will fail because stx
instruction will
not be generated in this case.
I look forward to your reply and suggestions on this matter.
Thanks,
zhaozhou.
