> Yes, it's supposed to be a start. > > Btw, after Robin now implemented "type punning" for gather/stride loads > to handle power-of-two size groups load/store-lanes needs similar > support which would esp. help ARM where there's only up to ld4(?).
>From what I heard so far nobody really likes segmented loads/stores (=load/store lanes) on the riscv hardware side anyway. On our design we have experimented with just replacing them with strided loads in the backend but that's not better either. So, yes, it's on my list but the impact on performance is not clear to me yet. -- Regards Robin
