On Wed, Nov 19, 2025 at 1:31 PM Robin Dapp <[email protected]> wrote: > > > Yes, it's supposed to be a start. > > > > Btw, after Robin now implemented "type punning" for gather/stride loads > > to handle power-of-two size groups load/store-lanes needs similar > > support which would esp. help ARM where there's only up to ld4(?). > > From what I heard so far nobody really likes segmented loads/stores > (=load/store lanes) on the riscv hardware side anyway. On our design > we have experimented with just replacing them with strided loads in > the backend but that's not better either. So, yes, it's on my list but > the impact on performance is not clear to me yet.
I'm aware of multiple designs that implement the unit-stride segment accesses with performance similar to unit-stride non-segment accesses, and implement the strided segment accesses at performance similar to strided non-segment accesses, provided the segments don't cross microarchitecturally significant boundaries. Like many of the more complex features in RVV, I'd expect more implementations to optimize these cases over time. > > -- > Regards > Robin >
