The preceding patches have fixed support for SME without SVE enabled, so
we can now remove the "sorry" for this configuration. This allows us to
remove SVE/SVE2 from the features that are added as a workaround when
trying to process a streaming function with SME disabled.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_override_options_internal):
Remove +sme+nosve sorry, and remove SVE from nosme workaround.
* doc/invoke.texi: Remove SVE2 requirement from +sme.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/no-sve-with-sme-1.c: Removed.
* gcc.target/aarch64/no-sve-with-sme-2.c: Removed.
* gcc.target/aarch64/no-sve-with-sme-3.c: Removed.
* gcc.target/aarch64/no-sve-with-sme-4.c: Removed.
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index
022b32ed27315078940618eaef56adee7328749d..34c48e5c1399053dad937642ee6b8306fa6b28c1
100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19475,10 +19475,7 @@ aarch64_override_options_internal (struct gcc_options
*opts)
" option %<-march%>, or by using the %<target%>"
" attribute or pragma", "sme");
opts->x_target_flags &= ~MASK_GENERAL_REGS_ONLY;
- auto new_flags = (isa_flags
- | feature_deps::SME ().enable
- /* TODO: Remove once we support SME without SVE2. */
- | feature_deps::SVE2 ().enable);
+ auto new_flags = isa_flags | feature_deps::SME ().enable;
aarch64_set_asm_isa_flags (opts, new_flags);
}
@@ -19611,12 +19608,6 @@ aarch64_override_options_internal (struct gcc_options
*opts)
& AARCH64_EXTRA_TUNE_DISPATCH_SCHED)
gcc_assert (aarch64_tune_params.dispatch_constraints != NULL);
- /* TODO: SME codegen without SVE2 is not supported, once this support is
added
- remove this 'sorry' and the implicit enablement of SVE2 in the checks for
- streaming mode above in this function. */
- if (TARGET_SME && !TARGET_SVE2)
- sorry ("no support for %qs without %qs", "sme", "sve2");
-
/* Set scalar costing to a high value such that we always pick
vectorization. Increase scalar costing by 10000%. */
if (opts->x_flag_aarch64_max_vectorization)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
e55797788d02db379d76d8ea4722f78c7acaec50..8b2a6c3dcec3e662fc4fcf3f8c74cf1acb15d680
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23067,8 +23067,7 @@ Enable the Common Short Sequence Compression
instructions.
Enable the shorter compare and branch instructions, @code{cbb}, @code{cbh} and
@code{cb}.
@item sme
-Enable the Scalable Matrix Extension. This is only supported when SVE2 is also
-enabled.
+Enable the Scalable Matrix Extension.
@item sme-i16i64
Enable the FEAT_SME_I16I64 extension to SME. This also enables SME
instructions.
diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c
b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c
deleted file mode 100644
index
e5bb2d95f65fc6d52c39d97187353e056cbb38a8..0000000000000000000000000000000000000000
--- a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-1.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* { dg-do compile } */
-/* { dg-skip-if "Do not override mcpu or march" { *-*-* } { -mcpu=* -march=* }
{ "" } } */
-/* { dg-options { "-march=armv8-a+sme" } } */
-/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" ""
{ target *-*-* } 0 } */
-int main (void)
-{
- return 0;
-}
diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c
b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c
deleted file mode 100644
index
13f09b37d724f6d73ef23dc563eb494d51c61033..0000000000000000000000000000000000000000
--- a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-2.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* { dg-do compile } */
-/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" ""
{ target *-*-* } 0 } */
-
-#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma")
-
-int main (void)
-{
- return 0;
-}
diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c
b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c
deleted file mode 100644
index
9e3cbeb6aeb5562e7eb5fab928144e3e4ca3cfd0..0000000000000000000000000000000000000000
--- a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-3.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* { dg-do compile } */
-/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" ""
{ target *-*-* } 0 } */
-
-int __attribute__ ((target( "arch=armv8.2-a+ssve-fp8fma"))) main (void)
-{
- return 0;
-}
-
diff --git a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c
b/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c
deleted file mode 100644
index
04a33a7b01b35adc5e20c0ccf9f6b1414cd7b52c..0000000000000000000000000000000000000000
--- a/gcc/testsuite/gcc.target/aarch64/no-sve-with-sme-4.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* { dg-do compile } */
-/* { dg-skip-if "Do not override mcpu or march" { *-*-* } { -mcpu=* -march=* }
{ "" } } */
-/* { dg-options { "-march=armv8-a" } } */
-/* { dg-message "sorry, unimplemented: no support for 'sme' without 'sve2'" ""
{ target *-*-* } 0 } */
-
-#pragma GCC target "+sme"
-
-int main (void)
-{
- return 0;
-}
