From: Stefan Schulze Frielinghaus <[email protected]> Single register constraints like hard register constraints or constraints associated with a single register class impose restrictions on optimizations when it comes to an interplay with hard registers. Since hard registers are not tracked by RA, except for liveness, they cannot be reloaded like pseudos. Therefore, optimizations must be carried out carefully not to introduce a conflict between a hard register and a pseudo which is constrained to the very same hard register.
Patch 3 is a bit WIP since there I'm making use of a sledge hammer. However, I still wanted to get this out and I'm seeking for some feedback. Since constraints associated with a single register class are not new, these kind of problems shouldn't be new and I guess have been solved here and there in the past. Thus, before polishing patch 3 up, I would like to make sure that there is not a more fancy way known. It is a bit annoying to deal with hard registers and pseudos which are assigned single register constraints all over the place. A pipe dream would be to get rid of hard registers prior RA. Fun fact: With patch 1 and 2 I'm finally able to build glibc for powerpc64le while using -fdemote-register-asm. I will post an update for that once I have ran all tests over multiple targets. Stefan Schulze Frielinghaus (3): ira: Implicit uses via hard register constraints cse: Take single register constraints into account combine: Skip in case of single register constraints [PR121426] gcc/combine.cc | 52 +++++++++++++++++++ gcc/cse.cc | 42 +++++++++++++++ gcc/ira-lives.cc | 7 +++ gcc/ira.cc | 6 +++ .../gcc.target/powerpc/asm-hard-reg-1.c | 10 ++++ .../gcc.target/powerpc/asm-hard-reg-2.c | 9 ++++ 6 files changed, 126 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/asm-hard-reg-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/asm-hard-reg-2.c -- 2.52.0
