Hi,
This is v2. The difference to before is that we now use separate insn
types (that need to be added everywhere).
As reported in PR123870 we miscompile an RVV-optimized jpeg-quantsmooth
with xtheadvector. The core issue is that we forget to emit a vsetvl
before a -fschedule-insn induced spill restore. Spills are usually
handled by full-register loads and stores but xtheadvector doesn't have
those. Instead, the regular loads and stores are used which differ from
full-register loads/store in the fact that they don't encode the LMUL
in the instruction directly and thus require a proper SEW and LMUL in
the vtype rather than just the ratio.
This patch adds th_vldr and th_vstr as new "type" attributes for
the xtheadvector full-register loads/stores.
I didn't manage to come up with a simple test case, though.
Regtested on rv64gcv_zvl512b.
Regards
Robin
PR target/123870
gcc/ChangeLog:
* config/riscv/riscv.md: Introduce th_vldr,th_vstr.
* config/riscv/thead-vector.md: Use for
pred_th_whole_mov.
* config/riscv/vector.md: Add to appropriate attributes.
* config/riscv/andes-23-series.md: Add th_vldr,thvstr.
* config/riscv/andes-25-series.md: Ditto.
* config/riscv/andes-45-series.md: Ditto.
* config/riscv/generic-vector-ooo.md: Ditto.
* config/riscv/mips-p8700.md: Ditto.
* config/riscv/sifive-7.md: Ditto.
* config/riscv/sifive-p400.md: Ditto.
* config/riscv/sifive-p600.md: Ditto.
* config/riscv/spacemit-x60.md: Ditto.
* config/riscv/tt-ascalon-d8.md: Ditto.
* config/riscv/xiangshan.md: Ditto.
---
gcc/config/riscv/andes-23-series.md | 1 +
gcc/config/riscv/andes-25-series.md | 2 +-
gcc/config/riscv/andes-45-series.md | 3 ++-
gcc/config/riscv/generic-vector-ooo.md | 4 ++--
gcc/config/riscv/mips-p8700.md | 2 +-
gcc/config/riscv/riscv.md | 5 ++++-
gcc/config/riscv/sifive-7.md | 4 ++--
gcc/config/riscv/sifive-p400.md | 2 +-
gcc/config/riscv/sifive-p600.md | 2 +-
gcc/config/riscv/spacemit-x60.md | 2 +-
gcc/config/riscv/thead-vector.md | 2 +-
gcc/config/riscv/tt-ascalon-d8.md | 4 ++--
gcc/config/riscv/vector.md | 16 ++++++++++------
gcc/config/riscv/xiangshan.md | 2 +-
14 files changed, 30 insertions(+), 21 deletions(-)
diff --git a/gcc/config/riscv/andes-23-series.md
b/gcc/config/riscv/andes-23-series.md
index e2da00140aa..398115072ee 100644
--- a/gcc/config/riscv/andes-23-series.md
+++ b/gcc/config/riscv/andes-23-series.md
@@ -172,6 +172,7 @@ (define_insn_reservation "andes_23_unknown" 1
vsm3me,vbrev,vctz,vgmul,vsha2ms,vaesz,vrev8,
vaeskf2,vsha2cl,vwsll,vaesdf,vaesem,vfwmaccbf16,
sf_vqmacc,sf_vc,sf_vc_se,sf_vfnrclip,vmsfs,vfwalu,
+ th_vldr,th_vstr,
vnshift,vldm,vslidedown,vicmp,vfcvtftoi,vmffs,vlsegdux,
vfredo,vstux,vsshift,vfwcvtbf16,vmpop,vicalu,vldff,
vislide1down,vstox,vfwcvtftof,vfmov,vislide1up,vldr,
diff --git a/gcc/config/riscv/andes-25-series.md
b/gcc/config/riscv/andes-25-series.md
index a649fa48a0b..23f1613876d 100644
--- a/gcc/config/riscv/andes-25-series.md
+++ b/gcc/config/riscv/andes-25-series.md
@@ -318,5 +318,5 @@ (define_insn_reservation "andes_25_vector_unknown" 1
vaeskf1,vandn,vaesdm,vclmul,vclmulh,vrol,vcpop,vbrev8,
vsm3me,vbrev,vctz,vgmul,vsha2ms,vaesz,vrev8,
vaeskf2,vsha2cl,vwsll,vaesdf,vaesem,vfwmaccbf16,
- sf_vqmacc,sf_vc,sf_vc_se,sf_vfnrclip"))
+ sf_vqmacc,sf_vc,sf_vc_se,sf_vfnrclip,th_vldr,th_vstr"))
"andes_25_vector_dummies")
diff --git a/gcc/config/riscv/andes-45-series.md
b/gcc/config/riscv/andes-45-series.md
index b379389e9b1..378180411cd 100644
--- a/gcc/config/riscv/andes-45-series.md
+++ b/gcc/config/riscv/andes-45-series.md
@@ -375,5 +375,6 @@ (define_insn_reservation "andes_45_vector_unknown" 1
vaeskf1,vandn,vaesdm,vclmul,vclmulh,vrol,vcpop,vbrev8,
vsm3me,vbrev,vctz,vgmul,vsha2ms,vaesz,vrev8,
vaeskf2,vsha2cl,vwsll,vaesdf,vaesem,vfwmaccbf16,
- sf_vqmacc,sf_vc,sf_vc_se,sf_vfnrclip,vlsegde"))
+ sf_vqmacc,sf_vc,sf_vc_se,sf_vfnrclip,vlsegde,
+ th_vldr,th_vstr"))
"andes_45_vector_dummies")
diff --git a/gcc/config/riscv/generic-vector-ooo.md
b/gcc/config/riscv/generic-vector-ooo.md
index 01bd25816cc..899e0130ac2 100644
--- a/gcc/config/riscv/generic-vector-ooo.md
+++ b/gcc/config/riscv/generic-vector-ooo.md
@@ -33,12 +33,12 @@ (define_cpu_unit "vxu_ooo_multicycle" "vector_ooo")
(define_insn_reservation "vec_load" 6
(and (eq_attr "tune" "generic_ooo,generic")
- (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
+ (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr,th_vldr"))
"vxu_ooo_issue,vxu_ooo_alu")
(define_insn_reservation "vec_store" 6
(and (eq_attr "tune" "generic_ooo,generic")
- (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
+ (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr,th_vstr"))
"vxu_ooo_issue,vxu_ooo_alu")
;; Vector segment loads/stores.
diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md
index cd3adb71821..09f9f53faf2 100644
--- a/gcc/config/riscv/mips-p8700.md
+++ b/gcc/config/riscv/mips-p8700.md
@@ -148,7 +148,7 @@ (define_insn_reservation "mips_p8700_unknown" 1
(and (eq_attr "tune" "mips_p8700")
(eq_attr "type" "rdvlenb,rdvl,wrvxrm,wrfrm,
rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
- vldux,vldox,vstux,vstox,vldff,vldr,vstr,
+ vldux,vldox,vstux,vstox,vldff,vldr,vstr,th_vldr,th_vstr,
vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
vimul,vidiv,viwmul,vimuladd,sf_vqmacc,viwmuladd,vimerge,vimov,
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 3fe0ad0ccdf..1447d6fb6d1 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -498,6 +498,9 @@ (define_attr "ext_enabled" "no,yes"
;; sf_vfnrclip vector fp32 to int8 ranged clip instructions
;; sf_vc vector coprocessor interface without side effect
;; sf_vc_se vector coprocessor interface with side effect
+;; XTheadVector specifics
+;; th_vldr vector whole register load instructions
+;; th_vstr vector whole register store instructions
(define_attr "type"
"unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore,
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
@@ -520,7 +523,7 @@ (define_attr "type"
vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,
vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz,
vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16,
- sf_vc,sf_vc_se"
+ sf_vc,sf_vc_se,th_vldr,th_vstr"
(cond [(eq_attr "got" "load") (const_string "load")
;; If a doubleword move uses these expensive instructions,
diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index 8db388901a0..b9e2d7e7e2c 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -186,13 +186,13 @@ (define_insn_reservation "sifive_7_vsetvl" 2
(define_insn_reservation "sifive_7_vec_load" 4
(and (eq_attr "tune" "sifive_7")
- (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr,
+ (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr,th_vldr,
vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff"))
"sifive_7_vcq,sifive_7_vl*3")
(define_insn_reservation "sifive_7_vec_store" 4
(and (eq_attr "tune" "sifive_7")
- (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr,
+ (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr,th_vstr,
vssegte,vssegts,vssegtux,vssegtox"))
"sifive_7_vcq,sifive_7_vs*3")
diff --git a/gcc/config/riscv/sifive-p400.md b/gcc/config/riscv/sifive-p400.md
index 0acdbdab31e..a619ffd7760 100644
--- a/gcc/config/riscv/sifive-p400.md
+++ b/gcc/config/riscv/sifive-p400.md
@@ -192,7 +192,7 @@ (define_bypass 1 "sifive_p400_f2i"
;; they are just dummies like this one.
(define_insn_reservation "sifive_p400_unknown" 1
(and (eq_attr "tune" "sifive_p400")
- (eq_attr "type"
"ghost,vfrecp,vclmul,vldm,vmffs,vclmulh,vlsegde,vfcvtitof,vsm4k,vfcvtftoi,vfdiv,vsm3c,vsm4r,viwmuladd,vfwredu,vcpop,vfwmuladd,vstux,vsshift,vfwcvtftof,vfncvtftof,vfwmaccbf16,vext,vssegte,rdvl,vaeskf1,vfslide1up,vmov,vimovvx,vaesef,vfsqrt,viminmax,vfwcvtftoi,vssegtox,vfclass,viwmul,vector,vgmul,vsm3me,vfcmp,vstm,vfredo,vfwmul,vaeskf2,vstox,vfncvtbf16,vislide1up,vgather,vldox,viwred,vctz,vghsh,vsts,vslidedown,vfmerge,vicmp,vsmul,vlsegdff,vfalu,vfmov,vislide1down,vfminmax,vcompress,vldr,vldff,vlsegdux,vimuladd,vsalu,vidiv,sf_vqmacc,vfslide1down,vaesem,vimerge,vfncvtftoi,vfwcvtitof,vicalu,vaesz,sf_vc_se,vsha2cl,vmsfs,vldux,vmidx,vslideup,vired,vlde,vfwredo,vfmovfv,vbrev,vfncvtitof,rdfrm,vsetvl,vssegts,vimul,vialu,vbrev8,vfwalu,rdvlenb,sf_vfnrclip,vclz,vnclip,sf_vc,vimov,vste,vfmuladd,vfmovvf,vwsll,vsetvl_pre,vlds,vlsegds,vmiota,vmalu,wrvxrm,wrfrm,viwalu,vaesdm,vssegtux,vaesdf,vimovxv,vror,vnshift,vstr,vaalu,vsha2ms,crypto,vfwcvtbf16,vlsegdox,vrol,vandn,vfsgnj,vmpop,vfredu,vsha2ch,vshift,vrev8,vfmul"))
+ (eq_attr "type"
"ghost,vfrecp,vclmul,vldm,vmffs,vclmulh,vlsegde,vfcvtitof,vsm4k,vfcvtftoi,vfdiv,vsm3c,vsm4r,viwmuladd,vfwredu,vcpop,vfwmuladd,vstux,vsshift,vfwcvtftof,vfncvtftof,vfwmaccbf16,vext,vssegte,rdvl,vaeskf1,vfslide1up,vmov,vimovvx,vaesef,vfsqrt,viminmax,vfwcvtftoi,vssegtox,vfclass,viwmul,vector,vgmul,vsm3me,vfcmp,vstm,vfredo,vfwmul,vaeskf2,vstox,vfncvtbf16,vislide1up,vgather,vldox,viwred,vctz,vghsh,vsts,vslidedown,vfmerge,vicmp,vsmul,vlsegdff,vfalu,vfmov,vislide1down,vfminmax,vcompress,vldr,th_vldr,vldff,vlsegdux,vimuladd,vsalu,vidiv,sf_vqmacc,vfslide1down,vaesem,vimerge,vfncvtftoi,vfwcvtitof,vicalu,vaesz,sf_vc_se,vsha2cl,vmsfs,vldux,vmidx,vslideup,vired,vlde,vfwredo,vfmovfv,vbrev,vfncvtitof,rdfrm,vsetvl,vssegts,vimul,vialu,vbrev8,vfwalu,rdvlenb,sf_vfnrclip,vclz,vnclip,sf_vc,vimov,vste,vfmuladd,vfmovvf,vwsll,vsetvl_pre,vlds,vlsegds,vmiota,vmalu,wrvxrm,wrfrm,viwalu,vaesdm,vssegtux,vaesdf,vimovxv,vror,vnshift,vstr,th_vstr,vaalu,vsha2ms,crypto,vfwcvtbf16,vlsegdox,vrol,vandn,vfsgnj,vmpop,vfredu,vsha2ch,vshift,vrev8,vfmul"))
"p400_int_pipe+sifive_p400_ialu")
diff --git a/gcc/config/riscv/sifive-p600.md b/gcc/config/riscv/sifive-p600.md
index ccd006d16ed..2f28626e81f 100644
--- a/gcc/config/riscv/sifive-p600.md
+++ b/gcc/config/riscv/sifive-p600.md
@@ -195,5 +195,5 @@ (define_bypass 1 "sifive_p600_f2i"
;; they are just dummies like this one.
(define_insn_reservation "sifive_p600_unknown" 1
(and (eq_attr "tune" "sifive_p600")
- (eq_attr "type"
"vicmp,vssegte,vbrev8,vfwalu,vimov,vmpop,vaesdf,vislide1up,vror,vsha2cl,vrol,vslideup,vimuladd,vclmul,vaesef,vext,vlsegdff,vfmuladd,vfclass,vmsfs,vfcmp,vsmul,vsm3me,vmalu,vshift,viwmuladd,vfslide1up,vlsegde,vsm4k,wrvxrm,vislide1down,vsm3c,vfwmuladd,vaesdm,vclmulh,vfwcvtftof,vfwredu,vfredo,sf_vfnrclip,vaesz,vwsll,vmiota,vctz,vsetvl_pre,vstm,vidiv,vssegtux,vfwmul,vcompress,vste,vired,vlsegds,vaesem,vfminmax,ghost,vandn,crypto,vfmul,vialu,vfmovvf,rdfrm,vldff,vfmerge,vsshift,vnclip,sf_vqmacc,vnshift,vfdiv,vfslide1down,vfncvtitof,vfsqrt,vimovxv,vstr,vfwcvtbf16,vfwcvtitof,vbrev,vssegtox,vssegts,vcpop,vmffs,viwmul,vldr,vmidx,rdvlenb,vfalu,vslidedown,vlde,vfsgnj,vfmov,viwalu,vsha2ch,vfncvtbf16,vfcvtitof,rdvl,vsetvl,vsha2ms,vector,vstux,vimerge,vclz,sf_vc,vfcvtftoi,viminmax,vsm4r,sf_vc_se,wrfrm,vstox,vfmovfv,vfncvtftoi,vimul,vsalu,vmov,vgmul,vgather,vldux,vlsegdox,vfncvtftof,vimovvx,vghsh,vldm,vldox,vfwcvtftoi,vlds,vfrecp,vaeskf2,vsts,vfredu,vicalu,vaalu,vfwmaccbf16,vrev8,vfwredo,vlsegdux,viwred,vaeskf1"))
+ (eq_attr "type"
"vicmp,vssegte,vbrev8,vfwalu,vimov,vmpop,vaesdf,vislide1up,vror,vsha2cl,vrol,vslideup,vimuladd,vclmul,vaesef,vext,vlsegdff,vfmuladd,vfclass,vmsfs,vfcmp,vsmul,vsm3me,vmalu,vshift,viwmuladd,vfslide1up,vlsegde,vsm4k,wrvxrm,vislide1down,vsm3c,vfwmuladd,vaesdm,vclmulh,vfwcvtftof,vfwredu,vfredo,sf_vfnrclip,vaesz,vwsll,vmiota,vctz,vsetvl_pre,vstm,vidiv,vssegtux,vfwmul,vcompress,vste,vired,vlsegds,vaesem,vfminmax,ghost,vandn,crypto,vfmul,vialu,vfmovvf,rdfrm,vldff,vfmerge,vsshift,vnclip,sf_vqmacc,vnshift,vfdiv,vfslide1down,vfncvtitof,vfsqrt,vimovxv,vstr,th_vstr,vfwcvtbf16,vfwcvtitof,vbrev,vssegtox,vssegts,vcpop,vmffs,viwmul,vldr,th_vldr,vmidx,rdvlenb,vfalu,vslidedown,vlde,vfsgnj,vfmov,viwalu,vsha2ch,vfncvtbf16,vfcvtitof,rdvl,vsetvl,vsha2ms,vector,vstux,vimerge,vclz,sf_vc,vfcvtftoi,viminmax,vsm4r,sf_vc_se,wrfrm,vstox,vfmovfv,vfncvtftoi,vimul,vsalu,vmov,vgmul,vgather,vldux,vlsegdox,vfncvtftof,vimovvx,vghsh,vldm,vldox,vfwcvtftoi,vlds,vfrecp,vaeskf2,vsts,vfredu,vicalu,vaalu,vfwmaccbf16,vrev8,vfwredo,vlsegdux,viwred,vaeskf1"))
"int_pipe+sifive_p600_ialu")
diff --git a/gcc/config/riscv/spacemit-x60.md b/gcc/config/riscv/spacemit-x60.md
index fdd7b87b394..51a9c0750f0 100644
--- a/gcc/config/riscv/spacemit-x60.md
+++ b/gcc/config/riscv/spacemit-x60.md
@@ -185,6 +185,6 @@ (define_insn_reservation "spacemit_x60_fdiv_double" 7
(define_insn_reservation "spacemi6_x60_dummy" 1
(and (eq_attr "tune" "spacemit_x60")
- (eq_attr "type"
"viminmax,vfmuladd,vfmovvf,vssegte,vlsegds,rdvlenb,vaesef,vfcmp,vmpop,vwsll,vsha2cl,vfwcvtbf16,vfncvtftoi,vgather,vsha2ch,vsts,vldm,vmsfs,vfmul,vcompress,vaesz,vssegtox,vstox,vclmulh,vghsh,vaalu,vslideup,vfalu,vaeskf1,vfcvtitof,vaesdm,vmffs,vandn,vstm,vgmul,vlds,viwmul,vfmerge,vlsegdff,vshift,vaesem,vaesdf,vste,ghost,viwred,vsalu,vfwredu,vmidx,sf_vfnrclip,vstux,vfslide1down,vfcvtftoi,vfncvtitof,vnshift,vsm3me,vired,vlde,vfwalu,sf_vc_se,vlsegdux,vicmp,vfncvtftof,vror,vfwmaccbf16,vfminmax,vldff,vstr,vsm3c,vfwcvtftoi,vbrev,vaeskf2,vidiv,vfwcvtftof,rdvl,vimul,vfsgnj,vimovvx,vsha2ms,vialu,vfredo,vctz,vlsegde,viwmuladd,vcpop,vsetvl,vldux,vfwmuladd,vector,wrvxrm,vsshift,vfredu,vimerge,vlsegdox,vfrecp,vnclip,vfclass,vbrev8,vslidedown,vldox,vmalu,vext,vimuladd,sf_vqmacc,vldr,vrol,vmov,vsmul,vclmul,vfmov,vislide1up,vssegtux,vclz,rdfrm,vfwcvtitof,vfncvtbf16,vfmovfv,vislide1down,vfwmul,vfsqrt,vrev8,vicalu,vimov,wrfrm,vfdiv,sf_vc,vsm4k,vmiota,vsm4r,viwalu,vsetvl_pre,vimovxv,vfwredo,vfslide1up,vssegts"))
+ (eq_attr "type"
"viminmax,vfmuladd,vfmovvf,vssegte,vlsegds,rdvlenb,vaesef,vfcmp,vmpop,vwsll,vsha2cl,vfwcvtbf16,vfncvtftoi,vgather,vsha2ch,vsts,vldm,vmsfs,vfmul,vcompress,vaesz,vssegtox,vstox,vclmulh,vghsh,vaalu,vslideup,vfalu,vaeskf1,vfcvtitof,vaesdm,vmffs,vandn,vstm,vgmul,vlds,viwmul,vfmerge,vlsegdff,vshift,vaesem,vaesdf,vste,ghost,viwred,vsalu,vfwredu,vmidx,sf_vfnrclip,vstux,vfslide1down,vfcvtftoi,vfncvtitof,vnshift,vsm3me,vired,vlde,vfwalu,sf_vc_se,vlsegdux,vicmp,vfncvtftof,vror,vfwmaccbf16,vfminmax,vldff,vstr,th_vstr,vsm3c,vfwcvtftoi,vbrev,vaeskf2,vidiv,vfwcvtftof,rdvl,vimul,vfsgnj,vimovvx,vsha2ms,vialu,vfredo,vctz,vlsegde,viwmuladd,vcpop,vsetvl,vldux,vfwmuladd,vector,wrvxrm,vsshift,vfredu,vimerge,vlsegdox,vfrecp,vnclip,vfclass,vbrev8,vslidedown,vldox,vmalu,vext,vimuladd,sf_vqmacc,vldr,th_vldr,vrol,vmov,vsmul,vclmul,vfmov,vislide1up,vssegtux,vclz,rdfrm,vfwcvtitof,vfncvtbf16,vfmovfv,vislide1down,vfwmul,vfsqrt,vrev8,vicalu,vimov,wrfrm,vfdiv,sf_vc,vsm4k,vmiota,vsm4r,viwalu,vsetvl_pre,vimovxv,vfwredo,vfslide1up,vssegts"))
"nothing")
diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md
index 5a02debdd20..86c78d2a0f0 100644
--- a/gcc/config/riscv/thead-vector.md
+++ b/gcc/config/riscv/thead-vector.md
@@ -122,7 +122,7 @@ (define_insn_and_split "@pred_th_whole_mov<mode>"
&& REGNO (operands[0]) == REGNO (operands[1])"
[(const_int 0)]
""
- [(set_attr "type" "vimov,vlds,vlds")
+ [(set_attr "type" "vimov,th_vldr,th_vstr")
(set_attr "mode" "<MODE>")
(set (attr "ta") (symbol_ref "riscv_vector::TAIL_UNDISTURBED"))
(set (attr "ma") (symbol_ref "riscv_vector::MASK_UNDISTURBED"))
diff --git a/gcc/config/riscv/tt-ascalon-d8.md
b/gcc/config/riscv/tt-ascalon-d8.md
index bd9efe5e824..c2a7f5be7c1 100644
--- a/gcc/config/riscv/tt-ascalon-d8.md
+++ b/gcc/config/riscv/tt-ascalon-d8.md
@@ -147,12 +147,12 @@ (define_insn_reservation "tt_ascalon_d8_popcount" 1
;; Vector loads and stores
(define_insn_reservation "tt_ascalon_d8_vec_load" 5
(and (eq_attr "tune" "tt_ascalon_d8")
- (eq_attr "type" "vlde,vldm,vldff,vldr"))
+ (eq_attr "type" "vlde,vldm,vldff,vldr,th_vldr"))
"tt_ascalon_d8_decode,tt_ascalon_d8_ls")
(define_insn_reservation "tt_ascalon_d8_vec_store" 5
(and (eq_attr "tune" "tt_ascalon_d8")
- (eq_attr "type" "vste,vstm,vstr"))
+ (eq_attr "type" "vste,vstm,vstr,th_vstr"))
"tt_ascalon_d8_decode,tt_ascalon_d8_ls")
(define_insn_reservation "tt_ascalon_d8_vec_load_strided" 16
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index faa7f071881..e0fd92c9015 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -56,7 +56,8 @@ (define_attr "has_vtype_op" "false,true"
vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
-
vfncvtbf16,vfwcvtbf16,vfwmaccbf16,sf_vqmacc,sf_vfnrclip,sf_vc,sf_vc_se")
+
vfncvtbf16,vfwcvtbf16,vfwmaccbf16,sf_vqmacc,sf_vfnrclip,sf_vc,sf_vc_se,\
+ th_vldr,th_vstr")
(const_string "true")]
(const_string "false")))
@@ -81,7 +82,8 @@ (define_attr "has_vl_op" "false,true"
vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
- vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
+ vfncvtbf16,vfwcvtbf16,vfwmaccbf16,\
+ th_vldr,th_vstr")
(const_string "true")]
(const_string "false")))
@@ -503,8 +505,9 @@ (define_attr "ratio" ""
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\
vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
(const_int INVALID_ATTRIBUTE)
- (and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\
- vlsegdff,vssegtux,vlsegdox,vlsegdux")
+ (and (eq_attr "type" "vlde,vste,th_vldr,th_vstr,vlsegde,vssegte,\
+ vlsegds,vssegts,vlsegdff,vssegtux,vlsegdox,\
+ vlsegdux")
(match_test "TARGET_XTHEADVECTOR"))
(const_int INVALID_ATTRIBUTE)
(eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
@@ -822,7 +825,7 @@ (define_attr "merge_op_idx" ""
vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh,\
- vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
+
vfncvtbf16,vfwcvtbf16,vfwmaccbf16,th_vldr,th_vstr")
(const_int 2)
(eq_attr "type"
"vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
@@ -842,7 +845,8 @@ (define_attr "mode_idx" ""
vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\
vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
-
vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz,vrol,vror")
+
vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz,vrol,vror,\
+ th_vldr,th_vstr")
(const_int 0)
(eq_attr "type" "vimovvx,vfmovvf")
diff --git a/gcc/config/riscv/xiangshan.md b/gcc/config/riscv/xiangshan.md
index 61791408781..c15480c75c3 100644
--- a/gcc/config/riscv/xiangshan.md
+++ b/gcc/config/riscv/xiangshan.md
@@ -107,7 +107,7 @@ (define_insn_reservation "xiangshan_alu" 1
;; they are just dummies like this one.
(define_insn_reservation "xiangshan_alu_unknown" 1
(and (eq_attr "tune" "xiangshan")
- (eq_attr "type"
"zicond,min,max,minu,maxu,clz,ctz,cpop,ghost,rotate,clmul,condmove,crypto,mvpair,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vstux,vstox,vldff,vldr,vstr,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,vimul,vidiv,viwmul,vimuladd,sf_vqmacc,viwmuladd,vimerge,vimov,vsalu,vaalu,vsmul,vsshift,vnclip,sf_vfnrclip,vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16,sf_vc,sf_vc_se"))
+ (eq_attr "type"
"zicond,min,max,minu,maxu,clz,ctz,cpop,ghost,rotate,clmul,condmove,crypto,mvpair,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vstux,vstox,vldff,vldr,th_vldr,vstr,th_vstr,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,vimul,vidiv,viwmul,vimuladd,sf_vqmacc,viwmuladd,vimerge,vimov,vsalu,vaalu,vsmul,vsshift,vnclip,sf_vfnrclip,vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16,sf_vc,sf_vc_se"))
"xs_alu_rs")
--
2.52.0
