>> sve and x86 would only have the inner mask-predicated insn. But I strongly >> prefer no nesting. > > So it would be sth like > > (vec_predicate:V4BI > (and:V4BI > (reg:V4BI ..) > (whilelt:V4BI (reg:SI ..))) > > for a combined mask (reg:V4BI) and length (reg:SI)? Or are you > thinking of "unstructured" (aka, sort-of-UNSPEC) > > (vec_predicate:V4BI > (reg:V4BI ...) > (reg:SI ...) > ... > > and on targets w/o length use, what, NULL_RTX?
Haven't converged on anything yet but my initial idea was indeed unstructured so it's easier to get length and mask. For non-length I would have gone with a global define VEC_PREDICATE_FULL_LEN = constm1_rtx or so. -- Regards Robin
