> I'd think a specific flag that indicates "never elide" for the vec_predicate > could help for that case. I just wonder how to properly annotate the > predicate. I'd be hesitant to add even more arguments/operand, even 5 as I > proposed is not currently supported out of the box. Maybe an otherwise > unused RTL flag can be repurposed? That might be too implicit, though?
Hmm, on the other hand, even for riscv we don't want the predicate to be elided. What I'd like is provably dead and side-effect free instructions (zero length, mask all false) to be deleted. Our actual vector insns are all described with a predicate and won't match without it. What we do is have the autovec expanders use unpredicated patterns. At the first split they are adorned with our unspec predicate. But that mechanism should go away and I'd much rather start out with predicates during expansion, at least for the optimizations that combine et al. can handle themselves. So my suggestion would instead be to set up the generic code in a way that "vec_predicate" would never be elided. -- Regards Robin
