From: Pan Li <[email protected]> The scalar unsigned SAT_MUL form 8, 9, 10 are supported already in previous. Therefore, add unit test to cover them.
The below test suites are passed for this patch series. * The rv64gcv fully regression test. Pan Li (3): RISC-V: Add test cases for scalar unsigned SAT form 8 RISC-V: Add test cases for scalar unsigned SAT form 9 RISC-V: Add test cases for scalar unsigned SAT form 10 .../gcc.target/riscv/sat/sat_arith.h | 38 +++++++++++++++++++ .../gcc.target/riscv/sat/sat_u_mul-10-u16.c | 11 ++++++ .../gcc.target/riscv/sat/sat_u_mul-10-u32.c | 11 ++++++ .../gcc.target/riscv/sat/sat_u_mul-10-u64.c | 11 ++++++ .../gcc.target/riscv/sat/sat_u_mul-10-u8.c | 11 ++++++ .../gcc.target/riscv/sat/sat_u_mul-11-u16.c | 11 ++++++ .../gcc.target/riscv/sat/sat_u_mul-11-u32.c | 11 ++++++ .../gcc.target/riscv/sat/sat_u_mul-11-u64.c | 11 ++++++ .../gcc.target/riscv/sat/sat_u_mul-11-u8.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u16-from-u128.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u16-from-u32.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u16-from-u64.rv32.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u16-from-u64.rv64.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u32-from-u128.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u32-from-u64.rv32.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u32-from-u64.rv64.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u64-from-u128.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u8-from-u128.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u8-from-u16.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u8-from-u32.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u8-from-u64.rv32.c | 11 ++++++ .../riscv/sat/sat_u_mul-9-u8-from-u64.rv64.c | 11 ++++++ .../riscv/sat/sat_u_mul-run-10-u16.c | 15 ++++++++ .../riscv/sat/sat_u_mul-run-10-u32.c | 15 ++++++++ .../riscv/sat/sat_u_mul-run-10-u64.c | 15 ++++++++ .../riscv/sat/sat_u_mul-run-10-u8.c | 15 ++++++++ .../riscv/sat/sat_u_mul-run-11-u16.c | 15 ++++++++ .../riscv/sat/sat_u_mul-run-11-u32.c | 15 ++++++++ .../riscv/sat/sat_u_mul-run-11-u64.c | 15 ++++++++ .../riscv/sat/sat_u_mul-run-11-u8.c | 15 ++++++++ .../riscv/sat/sat_u_mul-run-9-u16-from-u128.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u16-from-u32.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u16-from-u64.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u32-from-u128.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u32-from-u64.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u64-from-u128.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u8-from-u128.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u8-from-u16.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u8-from-u32.c | 16 ++++++++ .../riscv/sat/sat_u_mul-run-9-u8-from-u64.c | 16 ++++++++ 40 files changed, 549 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-10-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-10-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-10-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-10-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-11-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-11-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-11-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-11-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u16-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u16-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u16-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u32-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u32-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u8-from-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u8-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u8-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-9-u8-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-10-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-10-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-10-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-10-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-11-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-11-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-11-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-11-u8.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u16-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u16-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u32-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u8-from-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u8-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-9-u8-from-u64.c -- 2.43.0
