Hi,
Currently, reduc-6.c fails on the trunk when compiling for 32 bit.
We emit a DImode pred_extract_first of a V2SImode during legitimization
of a move. Normally, we would split that insn into two 32-bit extracts
but the splitter needs to be able to create pseudos which it can't
post reload. The insn here is emitted late, but during reload when we
can still create pseudos.
In order to protect against that situation, this patch just piggybacks on
the existing handling when no 64-bit vector elements are available
(!TARGET_VECTOR_ELEN64). That way, we don't emit 64-bit extracts and don't
need to rely on splitting late.
Regtested on rv64gcv_zvl512b. Going to push if the CI doesn't complain.
Regards
Robin
PR target/125097
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Emit 32-bit
vec_extracts right away.
---
gcc/config/riscv/riscv.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 681b816d248..742ea55be0f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3879,7 +3879,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx
src)
scalar_mode smode = as_a<scalar_mode> (mode);
unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size;
unsigned int num = known_eq (GET_MODE_SIZE (smode), 8)
- && !TARGET_VECTOR_ELEN_64 ? 2 : 1;
+ && (!TARGET_VECTOR_ELEN_64 || !TARGET_64BIT) ? 2 : 1;
bool need_int_reg_p = false;
if (num == 2)
--
2.53.0
