Add the XuanTie C950 (xt-c9501fdvt) as a known RISC-V CPU. The C950 is based on the rva23s64 profile with additional extensions.
gcc/ChangeLog: * config/riscv/riscv-cores.def: Add xt-c9501fdvt tune and core. * doc/riscv-mcpu.texi: Regenerated. * doc/riscv-mtune.texi: Regenerated. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-xt-c9501fdvt.c: New test. Signed-off-by: Wang Yaduo <[email protected]> --- gcc/config/riscv/riscv-cores.def | 10 ++ gcc/doc/riscv-mcpu.texi | 2 + gcc/doc/riscv-mtune.texi | 2 + .../gcc.target/riscv/mcpu-xt-c9501fdvt.c | 125 ++++++++++++++++++ 4 files changed, 139 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 257eae116..99d5963d1 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -48,6 +48,7 @@ RISCV_TUNE("xt-c910", generic, generic_ooo_tune_info) RISCV_TUNE("xt-c910v2", generic, generic_ooo_tune_info) RISCV_TUNE("xt-c920", generic, generic_ooo_tune_info) RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info) +RISCV_TUNE("xt-c9501fdvt", generic_ooo, generic_ooo_tune_info) RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) RISCV_TUNE("xiangshan-kunminghu", xiangshan, generic_ooo_tune_info) RISCV_TUNE("spacemit-x60", spacemit_x60, spacemit_x60_tune_info) @@ -150,6 +151,15 @@ RISCV_CORE("xt-c920v2", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_" "xtheadsync", "xt-c920v2") +RISCV_CORE("xt-c9501fdvt", "rva23s64_zfbfmin_zfh_zicfilp_zicfiss_zkr_zmmul_" + "zbc_zca_zcd_zabha_zacas_zama16b_zvbc_zvfbfmin_" + "zvfbfwma_zvfh_zvkb_zvkg_zvkn_zvknc_zvkned_" + "zvkng_zvknha_zvknhb_zvksc_zvksed_zvksg_zvksh_" + "zvl256b_smaia_smcntrpmf_smcsrind_smepmp_smmpm_" + "smnpm_smrnmi_ssaia_sscsrind_sspm_ssstrict_" + "svadu_svvptc", + "xt-c9501fdvt") + RISCV_CORE("tt-ascalon-d8", "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_" "zvfh_zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_" "smstateen_ssaia_ssstrict_svadu", diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi index f7b03a8f4..9ef9dd594 100644 --- a/gcc/doc/riscv-mcpu.texi +++ b/gcc/doc/riscv-mcpu.texi @@ -60,6 +60,8 @@ by particular CPU name. Permissible values for this option are: @samp{xt-c920v2}, +@samp{xt-c9501fdvt}, + @samp{tt-ascalon-d8}, @samp{xiangshan-nanhu}, diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi index 7ab6f6345..7aef8e63f 100644 --- a/gcc/doc/riscv-mtune.texi +++ b/gcc/doc/riscv-mtune.texi @@ -46,6 +46,8 @@ particular CPU name. Permissible values for this option are: @samp{xt-c920v2}, +@samp{xt-c9501fdvt}, + @samp{xiangshan-nanhu}, @samp{xiangshan-kunminghu}, diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c new file mode 100644 index 000000000..17e623fc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c9501fdvt.c @@ -0,0 +1,125 @@ +/* { dg-do compile { target { ! riscv_abi_e } } } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c9501fdvt" { target { rv64 } } } */ +/* XuanTie C950 => rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif + _zicclsm_ziccrse_zicfilp_zicfiss_zicntr_zicond_zicsr_zifencei + _zihintntl_zihintpause_zihpm_zimop_za64rs_zabha_zacas_zama16b + _zawrs_zfa_zfbfmin_zfh_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbc_zbs + _zkr_zkt_zmmul_zvbb_zvbc_zvfbfmin_zvfbfwma_zvfh_zvfhmin_zvkb + _zvkg_zvkn_zvknc_zvkned_zvkng_zvknha_zvknhb_zvksc_zvksed_zvksg + _zvksh_zvkt_zvl256b_shcounterenw_shgatpa_shtvala_shvsatpa + _shvstvala_shvstvecd_smaia_smcntrpmf_smcsrind_smepmp_smmpm_smnpm + _smrnmi_ssaia_ssccptr_sscofpmf_sscounterenw_sscsrind_ssnpm_sspm + _ssstateen_ssstrict_sstc_sstvala_sstvecd_ssu64xl_supm_svade + _svadu_svbare_svinval_svnapot_svpbmt_svvptc */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && (__riscv_flen == 64) \ + && defined(__riscv_i) \ + && defined(__riscv_m) \ + && defined(__riscv_a) \ + && defined(__riscv_f) \ + && defined(__riscv_d) \ + && defined(__riscv_c) \ + && defined(__riscv_b) \ + && defined(__riscv_v) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_ziccamoa) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicfilp) \ + && defined(__riscv_zicfiss) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zimop) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zabha) \ + && defined(__riscv_zacas) \ + && defined(__riscv_zama16b) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfbfmin) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zfhmin) \ + && defined(__riscv_zca) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcd) \ + && defined(__riscv_zcmop) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zkr) \ + && defined(__riscv_zkt) \ + && defined(__riscv_zmmul) \ + && defined(__riscv_zvbb) \ + && defined(__riscv_zvbc) \ + && defined(__riscv_zvfbfmin) \ + && defined(__riscv_zvfbfwma) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_zvfhmin) \ + && defined(__riscv_zvkb) \ + && defined(__riscv_zvkg) \ + && defined(__riscv_zvkn) \ + && defined(__riscv_zvknc) \ + && defined(__riscv_zvkned) \ + && defined(__riscv_zvkng) \ + && defined(__riscv_zvknha) \ + && defined(__riscv_zvknhb) \ + && defined(__riscv_zvksc) \ + && defined(__riscv_zvksed) \ + && defined(__riscv_zvksg) \ + && defined(__riscv_zvksh) \ + && defined(__riscv_zvkt) \ + && defined(__riscv_zvl256b) \ + && defined(__riscv_shcounterenw) \ + && defined(__riscv_shgatpa) \ + && defined(__riscv_shtvala) \ + && defined(__riscv_shvsatpa) \ + && defined(__riscv_shvstvala) \ + && defined(__riscv_shvstvecd) \ + && defined(__riscv_smaia) \ + && defined(__riscv_smcntrpmf) \ + && defined(__riscv_smcsrind) \ + && defined(__riscv_smepmp) \ + && defined(__riscv_smmpm) \ + && defined(__riscv_smnpm) \ + && defined(__riscv_smrnmi) \ + && defined(__riscv_ssaia) \ + && defined(__riscv_ssccptr) \ + && defined(__riscv_sscofpmf) \ + && defined(__riscv_sscounterenw) \ + && defined(__riscv_sscsrind) \ + && defined(__riscv_ssnpm) \ + && defined(__riscv_sspm) \ + && defined(__riscv_ssstateen) \ + && defined(__riscv_ssstrict) \ + && defined(__riscv_sstc) \ + && defined(__riscv_sstvala) \ + && defined(__riscv_sstvecd) \ + && defined(__riscv_ssu64xl) \ + && defined(__riscv_supm) \ + && defined(__riscv_svade) \ + && defined(__riscv_svadu) \ + && defined(__riscv_svbare) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_svvptc)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} -- 2.47.1
