On 5/15/2026 3:23 AM, Wang Yaduo wrote:
> Add the XuanTie C950 (xt-c9501fdvt) as a known RISC-V CPU. The C950
> is based on the rva23s64 profile with additional extensions.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-cores.def: Add xt-c9501fdvt tune and core.
> * doc/riscv-mcpu.texi: Regenerated.
> * doc/riscv-mtune.texi: Regenerated.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/mcpu-xt-c9501fdvt.c: New test.
>
> Signed-off-by: Wang Yaduo <[email protected]>
THanks. I've pushed this to the trunk.
Jeff
