From: Dhruv Chawla <[email protected]>
Signed-off-by: Dhruv Chawla <[email protected]>
gcc/ChangeLog:
* common/config/aarch64/aarch64-common.cc (aarch64_parse_cpu): Fix
typos.
* common/config/aarch64/cpuinfo.h: Likewise.
* config/aarch64/aarch64-builtins.cc: Likewise.
* config/aarch64/aarch64-c.cc (aarch64_pragma_target_parse): Likewise.
* config/aarch64/aarch64-modes.def (FLOAT_MODE): Likewise.
* config/aarch64/aarch64-simd.md: Likewise.
* config/aarch64/aarch64-speculation.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h: Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc (struct
binary_za_m_def): Likewise.
* config/aarch64/aarch64-sve-builtins.cc
(function_builder::add_function): Likewise.
* config/aarch64/aarch64-sve.md: Likewise.
* config/aarch64/aarch64-sve2.md: Likewise.
* config/aarch64/aarch64.cc (aarch64_init_sysregs): Likewise.
(aarch64_load_symref_appropriately): Likewise.
(aarch64_output_sve_cnt_immediate): Likewise.
(aarch64_replace_reg_mode): Likewise.
(aarch64_pass_by_reference_1): Likewise.
(aarch64_layout_arg): Likewise.
(aarch64_allocate_and_probe_stack_space): Likewise.
(aarch64_legitimize_address_displacement): Likewise.
(aarch64_output_casesi): Likewise.
(aarch64_stp_sequence_cost): Likewise.
(aarch64_vector_costs::add_stmt_cost): Likewise.
(aarch64_override_options): Likewise.
(aarch64_functions_b_resolvable_from_a): Likewise.
(dispatch_function_versions): Likewise.
(aarch64_can_inline_p): Likewise.
(aarch64_classify_symbol): Likewise.
(aarch64_build_builtin_va_list): Likewise.
(aarch64_sve_pred_valid_immediate): Likewise.
(aarch64_simd_lane_bounds): Likewise.
(aarch64_expand_vector_init_fallback): Likewise.
(aarch64_modes_compatible_p): Likewise.
(aarch64_ldrstr_offset_compare): Likewise.
(aarch64_speculation_safe_value): Likewise.
* config/aarch64/aarch64.h (DEFAULT_PCC_STRUCT_RETURN): Likewise.
(struct GTY): Likewise.
* config/aarch64/aarch64.md: Likewise.
* config/aarch64/aarch64.opt: Likewise.
* config/aarch64/arm_bf16.h: Likewise.
* config/aarch64/arm_neon.h (vbslq_u64): Likewise.
* config/aarch64/cortex-a57-fma-steering.cc: Likewise.
* config/aarch64/driver-aarch64.cc (get_cpu_from_id): Likewise.
(host_detect_local_cpu): Likewise.
* config/aarch64/iterators.md: Likewise.
* config/aarch64/thunderx.md: Likewise.
* config/aarch64/thunderx3t110.md: Likewise.
libgcc/ChangeLog:
* config/aarch64/aarch64-unwind.h (aarch64_demangle_return_addr): Fix
typos.
---
gcc/common/config/aarch64/aarch64-common.cc | 4 +-
gcc/common/config/aarch64/cpuinfo.h | 2 +-
gcc/config/aarch64/aarch64-builtins.cc | 2 +-
gcc/config/aarch64/aarch64-c.cc | 2 +-
gcc/config/aarch64/aarch64-modes.def | 2 +-
gcc/config/aarch64/aarch64-simd.md | 14 ++---
gcc/config/aarch64/aarch64-speculation.cc | 2 +-
.../aarch64/aarch64-sve-builtins-functions.h | 2 +-
.../aarch64/aarch64-sve-builtins-shapes.cc | 2 +-
gcc/config/aarch64/aarch64-sve-builtins.cc | 2 +-
gcc/config/aarch64/aarch64-sve.md | 8 +--
gcc/config/aarch64/aarch64-sve2.md | 2 +-
gcc/config/aarch64/aarch64.cc | 54 +++++++++----------
gcc/config/aarch64/aarch64.h | 10 ++--
gcc/config/aarch64/aarch64.md | 2 +-
gcc/config/aarch64/aarch64.opt | 2 +-
gcc/config/aarch64/arm_bf16.h | 2 +-
gcc/config/aarch64/arm_neon.h | 2 +-
gcc/config/aarch64/cortex-a57-fma-steering.cc | 2 +-
gcc/config/aarch64/driver-aarch64.cc | 4 +-
gcc/config/aarch64/iterators.md | 4 +-
gcc/config/aarch64/thunderx.md | 2 +-
gcc/config/aarch64/thunderx3t110.md | 2 +-
libgcc/config/aarch64/aarch64-unwind.h | 2 +-
24 files changed, 66 insertions(+), 66 deletions(-)
diff --git a/gcc/common/config/aarch64/aarch64-common.cc
b/gcc/common/config/aarch64/aarch64-common.cc
index ae467f140e3..e176262ea35 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -465,7 +465,7 @@ aarch64_parse_cpu (const char *to_parse, aarch64_cpu
*res_cpu,
if (ext_res != AARCH_PARSE_OK)
return ext_res;
}
- /* Extension parsing was successfull. Confirm the result
+ /* Extension parsing was successful. Confirm the result
cpu and ISA flags. */
*res_cpu = cpu->processor;
*res_flags = isa_flags;
@@ -711,7 +711,7 @@ aarch64_get_extension_string_for_isa_flags
for (auto alias: all_extensions)
{
/* Only allow "+nocrypto" when "sm4" is not already enabled
- (to avoid dependending on whether "+nocrypto" also disables "sm4"). */
+ (to avoid depending on whether "+nocrypto" also disables "sm4"). */
if (alias.flag_canonical == AARCH64_FL_CRYPTO
&& (current_flags & AARCH64_FL_SM4))
continue;
diff --git a/gcc/common/config/aarch64/cpuinfo.h
b/gcc/common/config/aarch64/cpuinfo.h
index a7955d08a89..9833c23798d 100644
--- a/gcc/common/config/aarch64/cpuinfo.h
+++ b/gcc/common/config/aarch64/cpuinfo.h
@@ -24,7 +24,7 @@
/* This enum is used in libgcc feature detection, and in the function
multiversioning implementation in aarch64.cc. The enum should use the same
- values as the corresponding enum in LLVM's compiler-rt, to faciliate
+ values as the corresponding enum in LLVM's compiler-rt, to facilitate
compatibility between compilers. */
enum CPUFeatures {
diff --git a/gcc/config/aarch64/aarch64-builtins.cc
b/gcc/config/aarch64/aarch64-builtins.cc
index 611f6dc45e0..b9cc2bf404f 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -593,7 +593,7 @@ static aarch64_simd_builtin_datum
aarch64_simd_builtin_data[] = {
CRC32_BUILTIN (crc32cw, SI) \
CRC32_BUILTIN (crc32cx, DI)
-/* The next 8 FCMLA instrinsics require some special handling compared the
+/* The next 8 FCMLA intrinsics require some special handling compared the
normal simd intrinsics. */
#define AARCH64_SIMD_FCMLA_LANEQ_BUILTINS \
FCMLA_LANEQ_BUILTIN (0, v2sf, fcmla, V2SF, false) \
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index 8da9163bc32..46417d71d41 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -384,7 +384,7 @@ aarch64_pragma_target_parse (tree args, tree pop_target)
cpp_opts->warn_unused_macros = saved_warn_unused_macros;
- /* If we're popping or reseting make sure to update the globals so that
+ /* If we're popping or resetting make sure to update the globals so that
the optab availability predicates get recomputed. */
if (pop_target)
aarch64_save_restore_target_globals (pop_target);
diff --git a/gcc/config/aarch64/aarch64-modes.def
b/gcc/config/aarch64/aarch64-modes.def
index d9bff61adec..a5785be19e4 100644
--- a/gcc/config/aarch64/aarch64-modes.def
+++ b/gcc/config/aarch64/aarch64-modes.def
@@ -263,7 +263,7 @@ FLOAT_MODE (TF, 16, ieee_quad_format);
/* A 4-tuple of SVE vectors with the maximum -msve-vector-bits= setting.
Note that this is a limit only on the compile-time sizes of modes;
it is not a limit on the runtime sizes, since VL-agnostic code
- must work with arbitary vector lengths. */
+ must work with arbitrary vector lengths. */
#define MAX_BITSIZE_MODE_ANY_MODE (2048 * 4)
/* Coefficient 1 is multiplied by the number of 128-bit chunks in an
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 7496da3a70c..1545c5cbbc7 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -579,7 +579,7 @@
})
;; These expands map to the Dot Product optab the vectorizer checks for
-;; and to the intrinsics patttern.
+;; and to the intrinsics pattern.
;; The auto-vectorizer expects a dot product builtin that also does an
;; accumulation into the provided register.
;; Given the following pattern
@@ -4509,7 +4509,7 @@
Example: UN<cc> (a, b) -> UNORDERED (a, b) |
(cm<cc> (isnan (a) ? 0.0 : a,
isnan (b) ? 0.0 : b))
- We use the following transformations for doing the comparisions:
+ We use the following transformations for doing the comparisons:
a UNGE b -> a GE b
a UNGT b -> a GT b
a UNLE b -> b GE a
@@ -4560,7 +4560,7 @@
break;
case LTGT:
- /* LTGT is not guranteed to not generate a FP exception. So let's
+ /* LTGT is not guaranteed to not generate a FP exception. So let's
go the faster way : ((a > b) || (b > a)). */
emit_insn (gen_aarch64_cmgt<mode> (operands[0],
operands[2], operands[3]));
@@ -7890,7 +7890,7 @@
;; ADDP with two registers semantically concatenates them and performs
;; a pairwise addition on the result. For 128-bit input modes represent this
-;; as a concatentation of the pairwise addition results of the two input
+;; as a concatenation of the pairwise addition results of the two input
;; registers. This allow us to avoid using intermediate 256-bit modes.
(define_insn "aarch64_addp<mode>_insn"
[(set (match_operand:VQ_I 0 "register_operand" "=w")
@@ -7914,7 +7914,7 @@
[(set_attr "type" "neon_reduc_add<q>")]
)
-;; For 64-bit input modes an ADDP is represented as a concatentation
+;; For 64-bit input modes an ADDP is represented as a concatenation
;; of the input registers into an 128-bit register which is then fed
;; into a pairwise add. That way we avoid having to create intermediate
;; 32-bit vector modes.
@@ -9405,7 +9405,7 @@
;; When AESE/AESMC fusion is enabled we really want to keep the two together
;; and enforce the register dependency without scheduling or register
-;; allocation messing up the order or introducing moves inbetween.
+;; allocation messing up the order or introducing moves in between.
;; Mash the two together during combine.
(define_insn "*aarch64_crypto_aese_fused"
@@ -9426,7 +9426,7 @@
;; When AESD/AESIMC fusion is enabled we really want to keep the two together
;; and enforce the register dependency without scheduling or register
-;; allocation messing up the order or introducing moves inbetween.
+;; allocation messing up the order or introducing moves in between.
;; Mash the two together during combine.
(define_insn "*aarch64_crypto_aesd_fused"
diff --git a/gcc/config/aarch64/aarch64-speculation.cc
b/gcc/config/aarch64/aarch64-speculation.cc
index a9a50abbdc2..47dcab3b265 100644
--- a/gcc/config/aarch64/aarch64-speculation.cc
+++ b/gcc/config/aarch64/aarch64-speculation.cc
@@ -148,7 +148,7 @@
mutually exclusive gates, with the normal pass being chosen wherever
possible. */
-/* Generate a code sequence to clobber SP if speculating incorreclty. */
+/* Generate a code sequence to clobber SP if speculating incorrectly. */
static rtx_insn *
aarch64_speculation_clobber_sp ()
{
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
index df5e44a294f..f1f082a50d3 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-functions.h
+++ b/gcc/config/aarch64/aarch64-sve-builtins-functions.h
@@ -371,7 +371,7 @@ typedef
unspec_based_function_exact_insn<code_for_aarch64_sve_add_lane>
typedef unspec_based_function_exact_insn<code_for_aarch64_sve_lane>
unspec_based_lane_function;
-/* A functon that uses aarch64_pred* patterns regardless of the
+/* A function that uses aarch64_pred* patterns regardless of the
predication type. */
typedef unspec_based_function_exact_insn<code_for_aarch64_pred>
unspec_based_pred_function;
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc
b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc
index 7d5376124e5..8611f20f6e8 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-shapes.cc
@@ -2059,7 +2059,7 @@ struct binary_za_m_def : public binary_za_m_base<>
build (function_builder &b, const function_group_info &group) const override
{
b.add_overloaded_functions (group, MODE_none);
- /* Allow the overloaded form to be specified seperately, with just
+ /* Allow the overloaded form to be specified separately, with just
a single suffix. This is necessary for the 64-bit SME MOP intrinsics,
which have some forms dependent on FEAT_SME_I16I64 and some forms
dependent on FEAT_SME_F64F64. The resolver needs to be defined
diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc
b/gcc/config/aarch64/aarch64-sve-builtins.cc
index d25e5437ba8..879c6052604 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
@@ -1514,7 +1514,7 @@ function_builder::add_function (const function_instance
&instance,
{
unsigned int length = vec_safe_length (registered_functions);
unsigned int code = (m_function_index << AARCH64_BUILTIN_SHIFT) |
AARCH64_BUILTIN_SVE;
- /* We need to be able to generate placeholders to enusre that we have a
+ /* We need to be able to generate placeholders to ensure that we have a
consistent numbering scheme for function codes between the C and C++
frontends, so that everything ties up in LTO.
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index 019630eb8d2..3b8e1c2e3cf 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -27,7 +27,7 @@
;; ---- Note on the handling of big-endian SVE
;; ---- Description of UNSPEC_PTEST
;; ---- Description of UNSPEC_PRED_Z
-;; ---- Note on predicated integer arithemtic and UNSPEC_PRED_X
+;; ---- Note on predicated integer arithmetic and UNSPEC_PRED_X
;; ---- Note on predicated FP arithmetic patterns and GP "strictness"
;; ---- Note on FFR handling
;;
@@ -305,7 +305,7 @@
;;
;; For example, when applying a separate PTEST to the result of a full-vector
;; .H comparison, the PTEST must be predicated on a .H PTRUE instead of a
-;; .B PTRUE. In constrast, the comparison might be predicated on either
+;; .B PTRUE. In contrast, the comparison might be predicated on either
;; a .H PTRUE or a .B PTRUE, since the values of odd-indexed predicate
;; bits don't matter for .H operations.
;;
@@ -336,7 +336,7 @@
;; The "Z" in UNSPEC_PRED_Z indicates that inactive lanes are zero.
;;
;; -------------------------------------------------------------------------
-;; ---- Note on predicated integer arithemtic and UNSPEC_PRED_X
+;; ---- Note on predicated integer arithmetic and UNSPEC_PRED_X
;; -------------------------------------------------------------------------
;;
;; Many SVE integer operations are predicated. We can generate them
@@ -8526,7 +8526,7 @@
;; it would would copy the upper (undefined) bits of each container along
;; with the corresponding defined bits. If SEL used the element size,
;; it would use separate predicate bits to select between the undefined
-;; elements in each input vector; these seperate predicate bits might
+;; elements in each input vector; these separate predicate bits might
;; themselves be undefined, depending on the mode of the predicate.
;;
;; Thus the only difference is whether the undefined bits in a container
diff --git a/gcc/config/aarch64/aarch64-sve2.md
b/gcc/config/aarch64/aarch64-sve2.md
index 4ceb8c784d9..46854c0c1da 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -4627,7 +4627,7 @@
;; When AESE/AESMC and AESD/AESIMC fusion is enabled, we really want
;; to keep the two together and enforce the register dependency without
;; scheduling or register allocation messing up the order or introducing
-;; moves inbetween. Mash the two together during combine.
+;; moves in between. Mash the two together during combine.
(define_insn "*aarch64_sve2_aese_fused"
[(set (match_operand:VNx16QI 0 "register_operand" "=w")
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 7b1dcbdbcfa..35a604a8ef8 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -579,7 +579,7 @@ aarch64_init_sysregs (void)
}
/* No direct access to the sysreg hash-map should be made. Doing so
- risks trying to acess an unitialized hash-map and dereferencing the
+ risks trying to access an uninitialized hash-map and dereferencing the
returned double pointer without due care risks dereferencing a
null-pointer. */
const sysreg_t *
@@ -3597,7 +3597,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
while the got entry is always of SImode size. The mode of
dest depends on how dest is used: if dest is assigned to a
pointer (e.g. in the memory), it has SImode; it may have
- DImode if dest is dereferenced to access the memeory.
+ DImode if dest is dereferenced to access the memory.
This is why we have to handle three different tlsie_small
patterns here (two patterns for ILP32). */
machine_mode mode = GET_MODE (dest);
@@ -4434,7 +4434,7 @@ aarch64_output_sve_cnt_immediate (const char *prefix,
const char *operands,
if (nelts_per_vq == 0)
/* There is some overlap in the ranges of the four CNT instructions.
Here we always use the smallest possible element size, so that the
- multiplier is 1 whereever possible. */
+ multiplier is 1 wherever possible. */
nelts_per_vq = factor & -factor;
int shift = std::min (exact_log2 (nelts_per_vq), 4);
gcc_assert (IN_RANGE (shift, 1, 4));
@@ -7059,7 +7059,7 @@ aarch64_replace_reg_mode (rtx x, machine_mode mode)
return x;
}
-/* Return the SVE REV[BHW] unspec for reversing quantites of mode MODE
+/* Return the SVE REV[BHW] unspec for reversing quantities of mode MODE
stored in wider integer containers. */
static unsigned int
@@ -7193,7 +7193,7 @@ aarch64_pass_by_reference_1 (CUMULATIVE_ARGS *pcum,
return false;
/* Arguments which are variable sized or larger than 2 registers are
- passed by reference unless they are a homogenous floating point
+ passed by reference unless they are a homogeneous floating point
aggregate. */
return size > 2 * UNITS_PER_WORD;
}
@@ -7762,7 +7762,7 @@ aarch64_layout_arg (cumulative_args_t pcum_v, const
function_arg_info &arg)
- Types bigger than 16 bytes are passed indirectly.
- If an argument of type T is passed indirectly, TYPE and MODE describe
- a pointer to T rather than T iself.
+ a pointer to T rather than T itself.
It follows that the AAPCS64 alignment of TYPE must be no greater
than 16 bytes.
@@ -7879,8 +7879,8 @@ aarch64_layout_arg (cumulative_args_t pcum_v, const
function_arg_info &arg)
nvrn = pcum->aapcs_nvrn;
- /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
- and homogenous short-vector aggregates (HVA). */
+ /* C1 - C5 for floating point, homogeneous floating point aggregates (HFA)
+ and homogeneous short-vector aggregates (HVA). */
if (allocate_nvrn)
{
/* aarch64_function_arg_alignment has never had an effect on
@@ -10314,7 +10314,7 @@ aarch64_allocate_and_probe_stack_space (rtx temp1, rtx
temp2,
The non-loop part won't be entered because if our allocation amount
doesn't require a loop, the case above would handle it.
- The residual amount won't be entered because TEMP1 is a mutliple of
+ The residual amount won't be entered because TEMP1 is a multiple of
the allocation size. The residual will always be 0. As such, the only
part we are actually using from that code is the loop setup. The
actual probing is done in aarch64_output_probe_stack_range. */
@@ -11885,7 +11885,7 @@ aarch64_legitimize_address_displacement (rtx *offset1,
rtx *offset2,
if (vec_flags & VEC_SVE_DATA)
/* LDR supports a 9-bit range, but the move patterns for
structure modes require all vectors to be in range of the
- same base. The simplest way of accomodating that while still
+ same base. The simplest way of accommodating that while still
promoting reuse of anchor points between different modes is
to use an 8-bit range unconditionally. */
vnum = ((vnum + 128) & 255) - 128;
@@ -14233,7 +14233,7 @@ aarch64_output_casesi (rtx *operands)
gcc_assert (index >= 0 && index <= 3);
- /* Need to implement table size reduction, by chaning the code below. */
+ /* Need to implement table size reduction, by changing the code below. */
output_asm_insn (patterns[index][0], operands);
ASM_GENERATE_INTERNAL_LABEL (label, "Lrtx", CODE_LABEL_NUMBER (operands[2]));
snprintf (buf, sizeof (buf),
@@ -16187,7 +16187,7 @@ cost_plus:
case UMOD:
if (speed)
{
- /* Slighly prefer UMOD over SMOD. */
+ /* Slightly prefer UMOD over SMOD. */
if (VECTOR_MODE_P (mode))
*cost += extra_cost->vect.alu;
else if (GET_MODE_CLASS (mode) == MODE_INT)
@@ -16208,7 +16208,7 @@ cost_plus:
/* There is no integer SQRT, so only DIV and UDIV can get
here. */
*cost += (extra_cost->mult[mode == DImode].idiv
- /* Slighly prefer UDIV over SDIV. */
+ /* Slightly prefer UDIV over SDIV. */
+ (code == DIV ? 1 : 0));
else
*cost += extra_cost->fp[mode == DFmode].div;
@@ -18565,7 +18565,7 @@ aarch64_stp_sequence_cost (unsigned int count,
vect_cost_for_stmt kind,
}
}
-/* Determine probabilistically whether the STMT is one tht could possible be
+/* Determine probabilistically whether the STMT is one that could possible be
made into a by lane operation later on. We can't be sure, but certain
operations have a higher chance. */
@@ -18894,7 +18894,7 @@ aarch64_vector_costs::add_stmt_cost (int count,
vect_cost_for_stmt kind,
/* If we're applying the SVE vs. Advanced SIMD unrolling heuristic,
estimate the number of statements in the unrolled Advanced SIMD
- loop. For simplicitly, we assume that one iteration of the
+ loop. For simplicity, we assume that one iteration of the
Advanced SIMD loop would need the same number of statements
as one iteration of the SVE loop. */
if (where == vect_body && m_unrolled_advsimd_niters)
@@ -20216,7 +20216,7 @@ aarch64_override_options (void)
{
/* If both -mcpu and -march are specified, warn if they are not
feature compatible. feature compatible means that the inclusion of the
- cpu features would end up disabling an achitecture feature. In
+ cpu features would end up disabling an architecture feature. In
otherwords the cpu features need to be a strict superset of the arch
features and if so prefer the -march ISA flags. */
if (~cpu_isa & arch_isa)
@@ -21422,7 +21422,7 @@ aarch64_functions_b_resolvable_from_a (tree decl_a,
tree decl_b, tree baseline)
if (b_version.is_valid ())
aarch64_parse_fmv_features (b_version, &isa_b, NULL, NULL, NULL);
- /* Are there any bits of b that arent in a. */
+ /* Are there any bits of b that aren't in a. */
if (isa_b & (~isa_a))
return false;
@@ -21736,7 +21736,7 @@ dispatch_function_versions (tree dispatch_decl,
gseq = bb_seq (*empty_bb);
/* Function version dispatch is via IFUNC. IFUNC resolvers fire before
- constructors, so explicity call __init_cpu_features_resolver here. */
+ constructors, so explicitly call __init_cpu_features_resolver here. */
tree init_fn_type = build_function_type_list (void_type_node,
long_unsigned_type_node,
build_ifunc_arg_type(),
@@ -22172,7 +22172,7 @@ aarch64_can_inline_p (tree caller, tree callee)
return false;
/* If the user explicitly specified -momit-leaf-frame-pointer for the
- caller and calle and they don't match up, reject inlining. */
+ caller and callee and they don't match up, reject inlining. */
if (!aarch64_tribools_ok_for_inlining_p (
caller_opts->x_flag_omit_leaf_frame_pointer,
callee_opts->x_flag_omit_leaf_frame_pointer,
@@ -22314,7 +22314,7 @@ aarch64_classify_symbol (rtx x, HOST_WIDE_INT offset)
the offset does not cause overflow of the final address. But
we have no way of knowing the address of symbol at compile time
so we can't accurately say if the distance between the PC and
- symbol + offset is outside the addressible range of +/-1MB in the
+ symbol + offset is outside the addressable range of +/-1MB in the
TINY code model. So we limit the maximum offset to +/-64KB and
assume the offset to the symbol is not larger than +/-(1MB - 64KB).
If offset_within_block_p is true we allow larger offsets. */
@@ -22543,7 +22543,7 @@ aarch64_build_builtin_va_list (void)
integer_type_node);
/* Tell tree-stdarg pass about our internal offset fields.
- NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
+ NOTE: va_list_gpr/fpr_counter_field are only used for tree comparison
purpose to identify whether the code is updating va_list internal
offset fields through irregular way. */
va_list_gpr_counter_field = f_groff;
@@ -24478,7 +24478,7 @@ aarch64_sve_pred_valid_immediate (rtx x,
simd_immediate_info *info)
'r' is an integer in the range -3 <= r <= 4.
Return true iff R represents a vale encodable into an AArch64 floating point
- move instruction as an immediate. Othewise false. */
+ move instruction as an immediate. Otherwise false. */
static bool
aarch64_real_float_const_representable_p (REAL_VALUE_TYPE r)
@@ -25218,7 +25218,7 @@ aarch64_simd_lane_bounds (rtx operand, HOST_WIDE_INT
low, HOST_WIDE_INT high,
}
}
-/* Peform endian correction on lane number N, which indexes a vector
+/* Perform endian correction on lane number N, which indexes a vector
of mode MODE, and return the result as an SImode rtx. */
rtx
@@ -25675,7 +25675,7 @@ aarch64_expand_vector_init_fallback (rtx target, rtx
vals)
/* This is a special vec_init<M><N> where N is not an element mode but a
vector mode with half the elements of M. We expect to find two entries
- of mode N in VALS and we must put their concatentation into TARGET. */
+ of mode N in VALS and we must put their concatenation into TARGET. */
if (XVECLEN (vals, 0) == 2 && VECTOR_MODE_P (GET_MODE (XVECEXP (vals, 0,
0))))
{
machine_mode narrow_mode = GET_MODE (XVECEXP (vals, 0, 0));
@@ -28773,7 +28773,7 @@ aarch64_modes_compatible_p (machine_mode mode1,
machine_mode mode2)
/* Implement TARGET_MODES_TIEABLE_P. In principle we should always defer
to aarch64_modes_compatible_p. However due to issues with register
- allocation it is preferable to avoid tieing integer scalar and FP
+ allocation it is preferable to avoid tying integer scalar and FP
scalar modes. Executing integer operations in general registers is
better than treating them as scalar vector operations. This reduces
latency and avoids redundant int<->FP moves. So tie modes if they
@@ -30159,7 +30159,7 @@ aarch64_ldrstr_offset_compare (const void *x, const
void *y)
stp w1, w1, [scratch, 0x8]
The peephole patterns detecting this opportunity should guarantee
- the scratch register is avaliable. */
+ the scratch register is available. */
bool
aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
@@ -30782,7 +30782,7 @@ aarch64_speculation_safe_value (machine_mode mode,
rtx result, rtx val, rtx failval)
{
/* Maybe we should warn if falling back to hard barriers. They are
- likely to be noticably more expensive than the alternative below. */
+ likely to be noticeably more expensive than the alternative below. */
if (!aarch64_track_speculation)
return default_speculation_safe_value (mode, result, val, failval);
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 681dff03bbf..0a71964a46e 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -1017,7 +1017,7 @@ extern enum aarch64_cpu aarch64_tune;
#define DEFAULT_PCC_STRUCT_RETURN 0
-/* The set of available Procedure Call Stardards. */
+/* The set of available Procedure Call Standards. */
enum arm_pcs
{
@@ -1078,12 +1078,12 @@ struct GTY (()) aarch64_frame
poly_int64 bytes_below_hard_fp;
/* The number of bytes between the top of the locals area and the top
- of the frame (the incomming SP). This value is always a multiple of
+ of the frame (the incoming SP). This value is always a multiple of
STACK_BOUNDARY. */
poly_int64 bytes_above_locals;
/* The number of bytes between the hard_frame_pointer and the top of
- the frame (the incomming SP). This value is always a multiple of
+ the frame (the incoming SP). This value is always a multiple of
STACK_BOUNDARY. */
poly_int64 bytes_above_hard_fp;
@@ -1478,7 +1478,7 @@ typedef struct
/* This definition should be relocated to aarch64-elf-raw.h. This macro
should be undefined in aarch64-linux.h and a clear_cache pattern
- implmented to emit either the call to __aarch64_sync_cache_range()
+ implemented to emit either the call to __aarch64_sync_cache_range()
directly or preferably the appropriate sycall or cache clear
instructions inline. */
#define CLEAR_INSN_CACHE(beg, end) \
@@ -1623,7 +1623,7 @@ extern poly_uint16 aarch64_sve_vg;
vectors in a structure mode (4).
This limit must not be used for variable-size vectors, since
- VL-agnostic code must work with arbitary vector lengths. */
+ VL-agnostic code must work with arbitrary vector lengths. */
#define MAX_COMPILE_TIME_VEC_BYTES (256 * 4)
#endif
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 9441e9d1eae..5567b43b65d 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4534,7 +4534,7 @@
;; umax (a, add (a, b)) => [sum, ovf] = adds (a, b); !ovf ? sum : a
;; umin (a, add (a, b)) => [sum, ovf] = adds (a, b); !ovf ? a : sum
-;; ... and the commutated versions:
+;; ... and the commuted versions:
;; umax (a, add (b, a)) => [sum, ovf] = adds (b, a); !ovf ? sum : a
;; umin (a, add (b, a)) => [sum, ovf] = adds (b, a); !ovf ? a : sum
(define_insn_and_split "*aarch64_plus_within_<optab><mode>3_<ovf_commutate>"
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index ef0d96e7486..deccc6c8887 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -463,7 +463,7 @@ trailing destructive updates of the base register used by a
pair.
-param=aarch64-tag-memory-loop-threshold=
Target Joined UInteger Var(aarch64_tag_memory_loop_threshold) Init(10)
IntegerRange(0, 65536) Param
-Param to control the treshold in number of granules beyond which an
+Param to control the threshold in number of granules beyond which an
explicit loop for tagging a memory block is emitted.
Wexperimental-fmv-target
diff --git a/gcc/config/aarch64/arm_bf16.h b/gcc/config/aarch64/arm_bf16.h
index 438a419da33..5da2ae85db2 100644
--- a/gcc/config/aarch64/arm_bf16.h
+++ b/gcc/config/aarch64/arm_bf16.h
@@ -1,4 +1,4 @@
-/* Arm BF16 instrinsics include file.
+/* Arm BF16 intrinsics include file.
Copyright (C) 2019-2026 Free Software Foundation, Inc.
Contributed by Arm.
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 82cf94b5173..2c4e24f4ad2 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -7003,7 +7003,7 @@ vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
return __builtin_aarch64_simd_bslv2di_uuuu (__a, __b, __c);
}
-/* ARMv8.1-A instrinsics. */
+/* ARMv8.1-A intrinsics. */
#pragma GCC push_options
#pragma GCC target ("+nothing+rdma")
diff --git a/gcc/config/aarch64/cortex-a57-fma-steering.cc
b/gcc/config/aarch64/cortex-a57-fma-steering.cc
index 6079b0679fe..2327160e428 100644
--- a/gcc/config/aarch64/cortex-a57-fma-steering.cc
+++ b/gcc/config/aarch64/cortex-a57-fma-steering.cc
@@ -44,7 +44,7 @@
/* For better performance, the destination of FMADD/FMSUB instructions should
have the same parity as their accumulator register if the accumulator
contains the result of a previous FMUL or FMADD/FMSUB instruction if
- targetting Cortex-A57 processors. Performance is also increased by
+ targeting Cortex-A57 processors. Performance is also increased by
otherwise keeping a good balance in the parity of the destination register
of FMUL or FMADD/FMSUB.
diff --git a/gcc/config/aarch64/driver-aarch64.cc
b/gcc/config/aarch64/driver-aarch64.cc
index a8888640e21..67920cc4076 100644
--- a/gcc/config/aarch64/driver-aarch64.cc
+++ b/gcc/config/aarch64/driver-aarch64.cc
@@ -120,7 +120,7 @@ get_cpu_from_id (const char* name)
return NULL;
}
-/* Check wether the CORE array is the same as the big.LITTLE BL_CORE.
+/* Check whether the CORE array is the same as the big.LITTLE BL_CORE.
For an example CORE={0xd08, 0xd03} and
BL_CORE=AARCH64_BIG_LITTLE (0xd08, 0xd03) will return true. */
@@ -436,7 +436,7 @@ host_detect_local_cpu (int argc, const char **argv)
: DEFAULT_ARCH);
auto arch_info = get_arch_from_id (arch_id);
- /* We got some arch indentifier that's not in aarch64-arches.def? */
+ /* We got some arch identifier that's not in aarch64-arches.def? */
if (!arch_info)
goto not_found;
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 39b1e84edcc..cd6da6df821 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -192,7 +192,7 @@
(HF "TARGET_SIMD_F16INST")
SF DF])
-;; Scalar and vetor modes for SF, DF.
+;; Scalar and vector modes for SF, DF.
(define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF])
;; Advanced SIMD single Float modes.
@@ -2526,7 +2526,7 @@
(V4x1DF "16") (V4x2DF "16")
(V4x4BF "16") (V4x8BF "16")])
-;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
+;; -fpic small model GOT reloc modifiers: gotpage_lo15/lo14 for ILP64/32.
;; No need of iterator for -fPIC as it use got_lo12 for both modes.
(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
index 612c7a1c9fb..b339f073564 100644
--- a/gcc/config/aarch64/thunderx.md
+++ b/gcc/config/aarch64/thunderx.md
@@ -59,7 +59,7 @@
(eq_attr "type" "csel"))
"thunderx_pipe0 | thunderx_pipe1")
-;; Multiply and mulitply accumulate and count leading zeros can only happen on
pipe 1
+;; Multiply and multiply accumulate and count leading zeros can only happen on
pipe 1
(define_insn_reservation "thunderx_mul" 4
(and (eq_attr "tune" "thunderx")
diff --git a/gcc/config/aarch64/thunderx3t110.md
b/gcc/config/aarch64/thunderx3t110.md
index f9a176fa491..8e3e90c1e32 100644
--- a/gcc/config/aarch64/thunderx3t110.md
+++ b/gcc/config/aarch64/thunderx3t110.md
@@ -535,7 +535,7 @@
; necessarily accurate (because insns are split into uops, and those
; may be issued out-of-order).
-; the LDP/LDNP imm-offset S/D/Q suppplies the first arg with latency 4
+; the LDP/LDNP imm-offset S/D/Q supplies the first arg with latency 4
; and the 2nd at 5 (Q form) or 8 (S/D form). Can this be modeled? These
;forms, as documented, do not use the I0/I1/I2 units (no I3), but the
; other LDP ones do.
diff --git a/libgcc/config/aarch64/aarch64-unwind.h
b/libgcc/config/aarch64/aarch64-unwind.h
index f67ee0045f3..1c309d971c9 100644
--- a/libgcc/config/aarch64/aarch64-unwind.h
+++ b/libgcc/config/aarch64/aarch64-unwind.h
@@ -154,7 +154,7 @@ aarch64_demangle_return_addr (struct _Unwind_Context
*context,
AArch64 DWARF instruction and contains a valid value, or is used to
describe the initial state set in aarch64_arch_extension_frame_init.
Return-address signing state is normally toggled by DW_CFA_AARCH64_negate
- _ra_state (also knwon by its alias as DW_CFA_GNU_window_save).
+ _ra_state (also known by its alias as DW_CFA_GNU_window_save).
However, RA state register can be set directly via DW_CFA_val_expression
too. GCC does not generate such CFI but some other compilers reportedly
do (see PR104689 for more details).
--
2.43.0
