From: Dhruv Chawla <[email protected]>
Signed-off-by: Dhruv Chawla <[email protected]>
gcc/ChangeLog:
* config/or1k/or1k.cc (or1k_strict_argument_naming): Fix typos.
(or1k_print_operand_address): Likewise.
* config/or1k/or1k.md: Likewise.
---
gcc/config/or1k/or1k.cc | 4 ++--
gcc/config/or1k/or1k.md | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/config/or1k/or1k.cc b/gcc/config/or1k/or1k.cc
index 66fd784f8b9..f1ecf21c6e2 100644
--- a/gcc/config/or1k/or1k.cc
+++ b/gcc/config/or1k/or1k.cc
@@ -1032,7 +1032,7 @@ or1k_strict_argument_naming (cumulative_args_t /* ca */)
/* Worker for TARGET_FUNCTION_ARG.
Return the next register to be used to hold a function argument or NULL_RTX
- if there's no more space. Arugment CUM_V represents the current argument
+ if there's no more space. Argument CUM_V represents the current argument
offset, zero for the first function argument. OpenRISC function arguments
maybe be passed in registers r3 to r8. */
@@ -1215,7 +1215,7 @@ or1k_print_operand_address (FILE *file, machine_mode, rtx
addr)
/* Worker for TARGET_PRINT_OPERAND.
Print operand X, an RTX, to the file FILE. The output is formed as expected
- by the OpenRISC assember. CODE is the letter following a '%' in an
+ by the OpenRISC assembler. CODE is the letter following a '%' in an
instrunction template used to control the RTX output. Example(s):
CODE RTX OUTPUT COMMENT
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index d3fbb209be7..7ab7f02bc5d 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -519,7 +519,7 @@
;; avoids 'convert_mode_scalar' from trying to do subregging
;; which we don't have support for.
;; We require signed and unsigned extend instructions because
-;; signed comparisons require signed extention, but for SR_F
+;; signed comparisons require signed extension, but for SR_F
;; it doesn't matter.
(define_expand "zero_extendbisi2_sr_f"
@@ -753,7 +753,7 @@
DONE;
})
-;; This is a placeholder, during RA, in order to create the PIC regiter.
+;; This is a placeholder, during RA, in order to create the PIC register.
;; We do this so that we don't unconditionally mark the LR register as
;; clobbered. It is replaced during prologue generation with the proper
;; set_got pattern below. This works because the set_got_tmp insn is the
@@ -797,7 +797,7 @@
;; Atomic Operations
;; -------------------------------------------------------------------------
-;; Note that MULT stands in for the non-existant NAND rtx_code.
+;; Note that MULT stands in for the non-existent NAND rtx_code.
(define_code_iterator FETCHOP [plus minus ior xor and mult])
(define_code_attr fetchop_name
--
2.43.0
