Tidy up a few non-functional issues in the RISC-V backend.
genrvv-type-indexer.cc includes <assert.h> but uses no assert, and
riscv-v.cc includes "targhooks.h" twice; remove both. In addition,
riscv_output_move and riscv_save_libcall_count call abort () where
gcc_unreachable () is the preferred idiom for unreachable points.
The remaining changes fix GNU coding style: add the missing space before
the open parenthesis of function calls and casts, fix brace placement,
remove a stray double semicolon and re-wrap a few over-long lines.
All of the above is redundant code, an idiom change or formatting, so
this is a cleanup with no functional change. No test case is added as
no behaviour changes.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Fix formatting.
* config/riscv/gen-riscv-mcpu-texi.cc: Likewise.
* config/riscv/gen-riscv-mtune-texi.cc: Likewise.
* config/riscv/genrvv-type-indexer.cc: Remove unused <assert.h>
include.
* config/riscv/riscv-string.cc: Fix formatting.
* config/riscv/riscv-target-attr.cc: Likewise.
* config/riscv/riscv-v.cc: Remove duplicate "targhooks.h" include.
Fix formatting.
* config/riscv/riscv-v.h: Fix formatting.
* config/riscv/riscv-vsetvl.cc: Likewise.
* config/riscv/riscv.cc (riscv_pass_by_reference): Remove stray
double semicolon. Fix formatting elsewhere.
(riscv_output_move): Use gcc_unreachable () instead of abort ().
(riscv_save_libcall_count): Use gcc_unreachable () instead of
abort ().
* config/riscv/riscv.h: Fix formatting.
* config/riscv/thead.cc: Likewise.
---
gcc/common/config/riscv/riscv-common.cc | 43 ++++++++++++------------
gcc/config/riscv/gen-riscv-mcpu-texi.cc | 12 +++----
gcc/config/riscv/gen-riscv-mtune-texi.cc | 5 ++-
gcc/config/riscv/genrvv-type-indexer.cc | 1 -
gcc/config/riscv/riscv-string.cc | 2 +-
gcc/config/riscv/riscv-target-attr.cc | 2 +-
gcc/config/riscv/riscv-v.cc | 7 ++--
gcc/config/riscv/riscv-v.h | 2 +-
gcc/config/riscv/riscv-vsetvl.cc | 31 +++++++++--------
gcc/config/riscv/riscv.cc | 27 ++++++++-------
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/thead.cc | 4 +--
12 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 8d6997bd9f6..0335cb26632 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -442,7 +442,6 @@ multi_letter_subset_rank (const std::string &subset)
break;
default:
gcc_unreachable ();
- return -1;
}
if (multiletter_class == 'z')
@@ -495,8 +494,8 @@ subset_cmp (const std::string &a, const std::string &b)
}
else
{
- int rank_a = multi_letter_subset_rank(a);
- int rank_b = multi_letter_subset_rank(b);
+ int rank_a = multi_letter_subset_rank (a);
+ int rank_b = multi_letter_subset_rank (b);
/* Using alphabetical/lexicographical order if they have same rank. */
if (rank_a == rank_b)
@@ -749,7 +748,7 @@ riscv_subset_list::to_string (bool version_p) const
if (!first &&
(version_p
|| subset->explicit_version_p
- || subset->name.length() > 1))
+ || subset->name.length () > 1))
oss << '_';
first = false;
@@ -894,19 +893,19 @@ riscv_subset_list::parse_profiles (const char *arch)
2. Mixed Profiles with other extensions
Use '_' to split Profiles and other extension. */
- std::string p(arch);
- const size_t p_len = p.size();
+ std::string p (arch);
+ const size_t p_len = p.size ();
for (int i = 0; riscv_profiles_table[i].profile_name != nullptr; ++i)
{
const std::string& p_name = riscv_profiles_table[i].profile_name;
const std::string& p_str = riscv_profiles_table[i].profile_string;
- size_t pos = p.find(p_name);
+ size_t pos = p.find (p_name);
/* Find profile at the begin. */
- if (pos == 0 && pos + p_name.size() <= p_len)
+ if (pos == 0 && pos + p_name.size () <= p_len)
{
- size_t after_pos = pos + p_name.size();
- std::string after_part = p.substr(after_pos);
+ size_t after_pos = pos + p_name.size ();
+ std::string after_part = p.substr (after_pos);
/* If there're only profile, return the profile_string directly. */
if (after_part[0] == '\0')
@@ -1135,7 +1134,7 @@ riscv_subset_list::handle_combine_ext ()
/* Add combine extensions */
if (is_combined)
{
- riscv_version_t ver = ext_info.default_version();
+ riscv_version_t ver = ext_info.default_version ();
add (ext_name.c_str (), ver.major_version,
ver.minor_version, false, true);
}
@@ -1367,8 +1366,8 @@ riscv_subset_list::parse (const char *arch, location_t
*loc)
riscv_subset_list *subset_list = new riscv_subset_list (arch, loc);
const char *p = arch;
- std::string a = subset_list->parse_profiles(p);
- p = subset_list->parse_base_ext (a.c_str());
+ std::string a = subset_list->parse_profiles (p);
+ p = subset_list->parse_base_ext (a.c_str ());
if (p == NULL)
goto fail;
@@ -1458,7 +1457,7 @@ riscv_arch_str (bool version_p)
if (cmdline_subset_list)
return cmdline_subset_list->to_string (version_p);
else
- return std::string();
+ return std::string ();
}
#define RISCV_EXT_FLAG_ENTRY(NAME, VAR, MASK) \
@@ -1825,7 +1824,7 @@ riscv_expand_arch_from_cpu (int argc ATTRIBUTE_UNUSED,
riscv_parse_arch_string (arch_str, NULL, loc);
const std::string arch = riscv_arch_str (false);
- return xasprintf ("-march=%s", arch.c_str());
+ return xasprintf ("-march=%s", arch.c_str ());
}
/* Report error if not found suitable multilib. */
@@ -2248,7 +2247,7 @@ riscv_arch_help (int, const char **)
/* Collect all exts, and sort it in canonical order. */
struct extension_comparator {
bool operator()(const std::string& a, const std::string& b) const {
- return subset_cmp(a, b) >= 1;
+ return subset_cmp (a, b) >= 1;
}
};
std::map<std::string, std::set<unsigned>, extension_comparator> all_exts;
@@ -2263,24 +2262,24 @@ riscv_arch_help (int, const char **)
}
}
- printf("All available -march extensions for RISC-V:\n");
- printf("\t%-20sVersion\n", "Name");
+ printf ("All available -march extensions for RISC-V:\n");
+ printf ("\t%-20sVersion\n", "Name");
for (auto const &ext_info : all_exts)
{
- printf("\t%-20s\t", ext_info.first.c_str());
+ printf ("\t%-20s\t", ext_info.first.c_str ());
bool first = true;
for (auto version : ext_info.second)
{
if (first)
first = false;
else
- printf(", ");
+ printf (", ");
unsigned major = version / RISCV_MAJOR_VERSION_BASE;
unsigned minor = (version % RISCV_MAJOR_VERSION_BASE)
/ RISCV_MINOR_VERSION_BASE;
- printf("%u.%u", major, minor);
+ printf ("%u.%u", major, minor);
}
- printf("\n");
+ printf ("\n");
}
exit (0);
}
diff --git a/gcc/config/riscv/gen-riscv-mcpu-texi.cc
b/gcc/config/riscv/gen-riscv-mcpu-texi.cc
index e9c7eb7ee9a..58845ee1110 100644
--- a/gcc/config/riscv/gen-riscv-mcpu-texi.cc
+++ b/gcc/config/riscv/gen-riscv-mcpu-texi.cc
@@ -31,13 +31,13 @@ main ()
#include "riscv-cores.def"
#undef RISCV_CORE
- for (size_t i = 0; i < coreNames.size(); ++i) {
- if (i == coreNames.size() - 1) {
- printf("@samp{%s}.\n", coreNames[i].c_str());
- } else {
- printf("@samp{%s},\n\n", coreNames[i].c_str());
+ for (size_t i = 0; i < coreNames.size (); ++i)
+ {
+ if (i == coreNames.size () - 1)
+ printf ("@samp{%s}.\n", coreNames[i].c_str ());
+ else
+ printf ("@samp{%s},\n\n", coreNames[i].c_str ());
}
- }
return 0;
}
diff --git a/gcc/config/riscv/gen-riscv-mtune-texi.cc
b/gcc/config/riscv/gen-riscv-mtune-texi.cc
index 5e42690c7a3..0aed2d6b679 100644
--- a/gcc/config/riscv/gen-riscv-mtune-texi.cc
+++ b/gcc/config/riscv/gen-riscv-mtune-texi.cc
@@ -31,9 +31,8 @@ main ()
#include "riscv-cores.def"
#undef RISCV_TUNE
- for (size_t i = 0; i < tuneNames.size(); ++i) {
- printf("@samp{%s},\n\n", tuneNames[i].c_str());
- }
+ for (size_t i = 0; i < tuneNames.size (); ++i)
+ printf ("@samp{%s},\n\n", tuneNames[i].c_str ());
puts ("and all valid options for @option{-mcpu=}.");
diff --git a/gcc/config/riscv/genrvv-type-indexer.cc
b/gcc/config/riscv/genrvv-type-indexer.cc
index 040a5aee9ac..ddc0d9863fc 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -20,7 +20,6 @@ along with GCC; see the file COPYING3. If not see
#include "coretypes.h"
-#include <assert.h>
#include <math.h>
#define BOOL_SIZE_LIST
\
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index e4f5c289f40..79e1dd03e5d 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -908,7 +908,7 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned
HOST_WIDE_INT length,
if (leftover)
riscv_block_move_straight (dest, src, leftover, align);
else
- emit_insn(gen_nop ());
+ emit_insn (gen_nop ());
}
/* Expand a cpymemsi instruction, which copies LENGTH bytes from
diff --git a/gcc/config/riscv/riscv-target-attr.cc
b/gcc/config/riscv/riscv-target-attr.cc
index 683b2a02f80..3628dbb9b1b 100644
--- a/gcc/config/riscv/riscv-target-attr.cc
+++ b/gcc/config/riscv/riscv-target-attr.cc
@@ -320,7 +320,7 @@ riscv_process_one_target_attr (char *arg_str,
}
std::unique_ptr<char[]> buf (new char[len+1]);
- char *str_to_check = buf.get();
+ char *str_to_check = buf.get ();
strcpy (str_to_check, arg_str);
/* Split attribute name from argument (if present). */
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2b2e346d0a..b0d2a1b966c 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -48,7 +48,6 @@
#include "optabs.h"
#include "tm-constrs.h"
#include "rtx-vector-builder.h"
-#include "targhooks.h"
#include "predict.h"
#include "errors.h"
#include "riscv-v.h"
@@ -1734,7 +1733,7 @@ expand_const_vector (rtx target, rtx src)
/* Support scalable const series vector. */
rtx base, step;
if (const_vec_series_p (src, &base, &step))
- return expand_const_vec_series(target, base, step);
+ return expand_const_vec_series (target, base, step);
/* Handle variable-length vector. */
unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN (src);
@@ -3858,7 +3857,7 @@ shuffle_slide_patterns (struct expand_vec_perm_d *d)
skip/slide over. For a slidedown it indicates how long
OP1's high part is, while the first element is the amount to slide. */
insn_code icode;
- int slide_cnt = slideup ? pivot : d->perm[0].to_constant();
+ int slide_cnt = slideup ? pivot : d->perm[0].to_constant ();
if (slideup)
{
rtx ops[] = {d->target, d->op0, d->op1, gen_int_mode (slide_cnt, Pmode)};
@@ -4396,7 +4395,7 @@ shuffle_generic_patterns (struct expand_vec_perm_d *d)
machine_mode sel_mode;
/* We don't enable SLP for non-power of 2 NPATTERNS. */
- if (!pow2p_hwi (d->perm.encoding().npatterns ()))
+ if (!pow2p_hwi (d->perm.encoding ().npatterns ()))
return false;
/* Disable shuffle if we can't find an appropriate integer index mode for
diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h
index 03714cca706..4b6db9eeb6b 100644
--- a/gcc/config/riscv/riscv-v.h
+++ b/gcc/config/riscv/riscv-v.h
@@ -83,7 +83,7 @@ private:
unsigned int m_inner_bytes_size;
};
-extern bool valid_vec_immediate_p(rtx);
+extern bool valid_vec_immediate_p (rtx);
} // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 16549c514dc..ac93bc07269 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3710,20 +3710,23 @@ pre_vsetvl::remove_unused_dest_operand ()
rtx vl = get_vl (rinsn);
vsetvl_info info = vsetvl_info (rinsn);
if (has_no_uses (cfg_bb, rinsn, REGNO (vl)))
- if (!info.has_vlmax_avl ())
- {
- rtx new_pat = info.get_vsetvl_pat (true);
- if (dump_file)
- {
- fprintf (dump_file,
- " Remove vsetvl insn %u's dest(vl) operand since "
- "it unused:\n",
- INSN_UID (rinsn));
- print_rtl_single (dump_file, rinsn);
- }
- validate_change_or_fail (rinsn, &PATTERN (rinsn), new_pat,
- false);
- }
+ {
+ if (!info.has_vlmax_avl ())
+ {
+ rtx new_pat = info.get_vsetvl_pat (true);
+ if (dump_file)
+ {
+ fprintf (dump_file,
+ " Remove vsetvl insn %u's dest(vl) operand"
+ " since "
+ "it unused:\n",
+ INSN_UID (rinsn));
+ print_rtl_single (dump_file, rinsn);
+ }
+ validate_change_or_fail (rinsn, &PATTERN (rinsn), new_pat,
+ false);
+ }
+ }
}
}
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6c69134f337..18d6d52b5f3 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -167,7 +167,7 @@ struct GTY(()) riscv_frame_info {
poly_int64 arg_pointer_offset;
/* Reset this struct, clean all field to zero. */
- void reset(void);
+ void reset (void);
};
enum riscv_privilege_levels {
@@ -1009,7 +1009,7 @@ typedef enum
typedef insn_code (*code_for_push_pop_t) (machine_mode);
-void riscv_frame_info::reset(void)
+void riscv_frame_info::reset (void)
{
total_size = 0;
mask = 0;
@@ -2060,7 +2060,7 @@ riscv_float_const_rtx_index_for_fli (rtx x)
machine_mode mode = GET_MODE (x);
if (!TARGET_ZFA
- || !CONST_DOUBLE_P(x)
+ || !CONST_DOUBLE_P (x)
|| mode == VOIDmode
|| (mode == HFmode && !(TARGET_ZFH || TARGET_ZVFH))
|| (mode == SFmode && !TARGET_HARD_FLOAT)
@@ -5305,7 +5305,7 @@ riscv_output_move (rtx dest, rtx src)
return "bseti\t%0,zero,%S1";
/* Should never reach here. */
- abort ();
+ gcc_unreachable ();
}
if (src_code == HIGH)
@@ -7324,7 +7324,7 @@ riscv_libcall_value (machine_mode mode, const_rtx fun
ATTRIBUTE_UNUSED)
static bool
riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg)
{
- HOST_WIDE_INT size = arg.type_size_in_bytes ().to_constant ();;
+ HOST_WIDE_INT size = arg.type_size_in_bytes ().to_constant ();
struct riscv_arg_info info;
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
@@ -8170,7 +8170,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
if (letter == '~')
{
if (TARGET_64BIT)
- fputc('w', file);
+ fputc ('w', file);
return;
}
machine_mode mode = GET_MODE (op);
@@ -8896,7 +8896,7 @@ riscv_save_libcall_count (unsigned mask)
for (unsigned n = GP_REG_LAST; n > GP_REG_FIRST; n--)
if (BITSET_P (mask, n))
return CALLEE_SAVED_REG_NUMBER (n) + 1;
- abort ();
+ gcc_unreachable ();
}
/* calculate number of s regs in multi push and pop.
@@ -9020,7 +9020,7 @@ riscv_compute_frame_info (void)
interrupt_save_prologue_temp = true;
}
- frame->reset();
+ frame->reset ();
if (!cfun->machine->naked_p)
{
@@ -9266,8 +9266,9 @@ riscv_set_return_address (rtx address, rtx scratch)
rtx slot_address;
gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
- slot_address = riscv_add_offset (scratch, stack_pointer_rtx,
-
cfun->machine->frame.gp_sp_offset.to_constant());
+ slot_address
+ = riscv_add_offset (scratch, stack_pointer_rtx,
+ cfun->machine->frame.gp_sp_offset.to_constant ());
riscv_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
}
@@ -9585,7 +9586,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame,
poly_int64 remaining_siz
poly_int64 callee_saved_first_step =
remaining_size - frame->frame_pointer_offset;
- gcc_assert(callee_saved_first_step.is_constant ());
+ gcc_assert (callee_saved_first_step.is_constant ());
HOST_WIDE_INT min_first_step =
riscv_stack_align (callee_saved_first_step.to_constant ());
HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8;
@@ -9667,7 +9668,7 @@ riscv_adjust_multi_push_cfi_prologue (int saved_size)
unsigned int num_multi_push = riscv_multi_push_regs_count (mask);
for (unsigned int i = 0; i < num_multi_push; i++) {
- gcc_assert(zcmp_save_reg_order[i] != INVALID_REGNUM);
+ gcc_assert (zcmp_save_reg_order[i] != INVALID_REGNUM);
mask |= 1 << (zcmp_save_reg_order[i] - GP_REG_FIRST);
}
@@ -11679,7 +11680,7 @@ riscv_output_mi_thunk (FILE *file, tree thunk_fndecl
ATTRIBUTE_UNUSED,
emit_note (NOTE_INSN_PROLOGUE_END);
if (is_zicfilp_p ())
- emit_insn(gen_lpad (const0_rtx));
+ emit_insn (gen_lpad (const0_rtx));
/* Determine if we can use a sibcall to call FUNCTION directly. */
fnaddr = gen_rtx_MEM (FUNCTION_MODE, XEXP (DECL_RTL (function), 0));
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index fccf9e6dc09..c2e5551aeaf 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -901,7 +901,7 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
#undef ASM_OUTPUT_OPCODE
#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
- (PTR) = riscv_asm_output_opcode(STREAM, PTR)
+ (PTR) = riscv_asm_output_opcode (STREAM, PTR)
#define JUMP_TABLES_IN_TEXT_SECTION (riscv_cmodel == CM_LARGE)
#define CASE_VECTOR_MODE SImode
diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index 1f25af96e7f..b143900939d 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -702,7 +702,7 @@ th_memidx_classify_address_index (struct riscv_address_info
*info, rtx x,
&& GET_MODE (XEXP (offset, 0)) == DImode
&& GET_MODE (XEXP (XEXP (offset, 0), 0)) == SImode
&& CONST_INT_P (XEXP (offset, 1))
- && IN_RANGE(INTVAL (XEXP (offset, 1)), 0, 3))
+ && IN_RANGE (INTVAL (XEXP (offset, 1)), 0, 3))
{
type = (GET_CODE (XEXP (offset, 0)) == SIGN_EXTEND)
? ADDRESS_REG_REG : ADDRESS_REG_UREG;
@@ -1224,7 +1224,7 @@ th_print_operand_address (FILE *file, machine_mode mode,
rtx x)
/* Number array of registers X1, X5-X7, X10-X17, X28-X31, to be
operated on by instruction th.ipush/th.ipop in XTheadInt. */
-int th_int_regs[] ={
+int th_int_regs[] = {
RETURN_ADDR_REGNUM,
T0_REGNUM, T1_REGNUM, T2_REGNUM,
A0_REGNUM, A1_REGNUM, A2_REGNUM, A3_REGNUM,
--
2.52.0
