Re: [PATCH 2/2] RISC-V: Fix typos in comments and a misspelled variable

[Kito Cheng]

LGTM

Jin Ma <ji...@linux.alibaba.com> 於 2026年6月2日週二 上午11:15寫道：
>
> Fix comment typos, grammatical errors and GNU two-space sentence
> spacing across the RISC-V backend.  Also rename the misspelled local
> variable additioanl_bytes in riscv_zcmp_valid_stack_adj_bytes_p to
> additional_bytes.
>
> The change is limited to comments and a local variable name, so this
> is a non-functional change.  No test case is added as no behaviour
> changes.
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.cc: Fix typos in comments.
>         * config/riscv/andes-25-series.md: Likewise.
>         * config/riscv/autovec-opt.md: Likewise.
>         * config/riscv/autovec.md: Likewise.
>         * config/riscv/bitmanip.md: Likewise.
>         * config/riscv/constraints.md: Likewise.
>         * config/riscv/gen-riscv-ext-opt.cc: Likewise.
>         * config/riscv/gen-riscv-mcpu-texi.cc: Likewise.
>         * config/riscv/generic-vector-ooo.md: Likewise.
>         * config/riscv/multilib-generator: Likewise.
>         * config/riscv/riscv-avlprop.cc: Likewise.
>         * config/riscv/riscv-bclr-lowest-set-bit.cc: Likewise.
>         * config/riscv/riscv-ext-andes.def: Likewise.
>         * config/riscv/riscv-ext.def: Likewise.
>         * config/riscv/riscv-ext.opt: Likewise.
>         * config/riscv/riscv-modes.def: Likewise.
>         * config/riscv/riscv-opt-popretz.cc: Likewise.
>         * config/riscv/riscv-profiles.def: Likewise.
>         * config/riscv/riscv-protos.h: Likewise.
>         * config/riscv/riscv-selftests.cc: Likewise.
>         * config/riscv/riscv-sr.cc: Likewise.
>         * config/riscv/riscv-string.cc: Likewise.
>         * config/riscv/riscv-subset.h: Likewise.
>         * config/riscv/riscv-target-attr.cc: Likewise.
>         * config/riscv/riscv-v.cc: Likewise.
>         * config/riscv/riscv-vect-permconst.cc: Likewise.
>         * config/riscv/riscv-vector-builtins-bases.cc: Likewise.
>         * config/riscv/riscv-vector-builtins-functions.def: Likewise.
>         * config/riscv/riscv-vector-builtins-shapes.cc: Likewise.
>         * config/riscv/riscv-vector-builtins-types.def: Likewise.
>         * config/riscv/riscv-vector-builtins.cc: Likewise.
>         * config/riscv/riscv-vector-builtins.def: Likewise.
>         * config/riscv/riscv-vector-builtins.h: Likewise.
>         * config/riscv/riscv-vector-costs.cc: Likewise.
>         * config/riscv/riscv-vector-costs.h: Likewise.
>         * config/riscv/riscv-vsetvl.cc: Likewise.
>         * config/riscv/riscv-vsetvl.def: Likewise.
>         * config/riscv/riscv-zicfilp.cc: Likewise.
>         * config/riscv/riscv.cc: Likewise.
>         (riscv_zcmp_valid_stack_adj_bytes_p): Rename misspelled
>         variable additioanl_bytes to additional_bytes.
>         * config/riscv/riscv.h: Likewise.
>         * config/riscv/riscv.md: Likewise.
>         * config/riscv/sifive-vector-builtins-functions.def: Likewise.
>         * config/riscv/sifive_vector.h: Likewise.
>         * config/riscv/spacemit-x60.md: Likewise.
>         * config/riscv/thead.cc: Likewise.
>         * config/riscv/tt-ascalon-d8.md: Likewise.
>         * config/riscv/vector-crypto.md: Likewise.
>         * config/riscv/vector-iterators.md: Likewise.
>         * config/riscv/vector.md: Likewise.
>         * config/riscv/zicond.md: Likewise.
>         * doc/riscv-mcpu.texi: Regenerate.
> ---
>  gcc/common/config/riscv/riscv-common.cc       | 10 +--
>  gcc/config/riscv/andes-25-series.md           |  8 +-
>  gcc/config/riscv/autovec-opt.md               | 14 +--
>  gcc/config/riscv/autovec.md                   |  4 +-
>  gcc/config/riscv/bitmanip.md                  |  6 +-
>  gcc/config/riscv/constraints.md               |  2 +-
>  gcc/config/riscv/gen-riscv-ext-opt.cc         |  2 +-
>  gcc/config/riscv/gen-riscv-mcpu-texi.cc       |  2 +-
>  gcc/config/riscv/generic-vector-ooo.md        |  2 +-
>  gcc/config/riscv/multilib-generator           |  8 +-
>  gcc/config/riscv/riscv-avlprop.cc             | 10 +--
>  gcc/config/riscv/riscv-ext.def                |  2 +-
>  gcc/config/riscv/riscv-ext.opt                |  2 +-
>  gcc/config/riscv/riscv-modes.def              |  8 +-
>  gcc/config/riscv/riscv-opt-popretz.cc         |  4 +-
>  gcc/config/riscv/riscv-profiles.def           |  2 +-
>  gcc/config/riscv/riscv-protos.h               | 14 +--
>  gcc/config/riscv/riscv-selftests.cc           |  4 +-
>  gcc/config/riscv/riscv-sr.cc                  |  2 +-
>  gcc/config/riscv/riscv-string.cc              |  4 +-
>  gcc/config/riscv/riscv-subset.h               |  2 +-
>  gcc/config/riscv/riscv-target-attr.cc         |  4 +-
>  gcc/config/riscv/riscv-v.cc                   | 61 ++++++-------
>  gcc/config/riscv/riscv-vect-permconst.cc      |  2 +-
>  .../riscv/riscv-vector-builtins-bases.cc      |  2 +-
>  .../riscv/riscv-vector-builtins-functions.def |  8 +-
>  .../riscv/riscv-vector-builtins-shapes.cc     | 14 +--
>  .../riscv/riscv-vector-builtins-types.def     |  4 +-
>  gcc/config/riscv/riscv-vector-builtins.cc     | 62 ++++++-------
>  gcc/config/riscv/riscv-vector-builtins.def    | 20 ++---
>  gcc/config/riscv/riscv-vector-builtins.h      | 12 +--
>  gcc/config/riscv/riscv-vector-costs.cc        |  4 +-
>  gcc/config/riscv/riscv-vector-costs.h         |  2 +-
>  gcc/config/riscv/riscv-vsetvl.cc              | 59 ++++++------
>  gcc/config/riscv/riscv-vsetvl.def             |  6 +-
>  gcc/config/riscv/riscv-zicfilp.cc             |  8 +-
>  gcc/config/riscv/riscv.cc                     | 89 ++++++++++---------
>  gcc/config/riscv/riscv.h                      |  5 +-
>  gcc/config/riscv/riscv.md                     | 10 +--
>  .../sifive-vector-builtins-functions.def      |  4 +-
>  gcc/config/riscv/sifive_vector.h              |  2 +-
>  gcc/config/riscv/spacemit-x60.md              |  2 +-
>  gcc/config/riscv/thead.cc                     | 20 ++---
>  gcc/config/riscv/tt-ascalon-d8.md             |  2 +-
>  gcc/config/riscv/vector-crypto.md             |  2 +-
>  gcc/config/riscv/vector-iterators.md          |  2 +-
>  gcc/config/riscv/vector.md                    | 40 +++++----
>  gcc/config/riscv/zicond.md                    |  8 +-
>  gcc/doc/riscv-mcpu.texi                       |  2 +-
>  49 files changed, 288 insertions(+), 280 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 0335cb26632..e483e2bdd79 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -352,7 +352,7 @@ riscv_subset_list::~riscv_subset_list ()
>      }
>  }
>
> -/* Compute the match score of two arch string, return 0 if incompatible.  */
> +/* Compute the match score of two arch strings, return 0 if incompatible.  */
>  int
>  riscv_subset_list::match_score (riscv_subset_list *list) const
>  {
> @@ -497,7 +497,7 @@ subset_cmp (const std::string &a, const std::string &b)
>        int rank_a = multi_letter_subset_rank (a);
>        int rank_b = multi_letter_subset_rank (b);
>
> -      /* Using alphabetical/lexicographical order if they have same rank.  */
> +      /* Use alphabetical/lexicographical order if they have the same rank.  
> */
>        if (rank_a == rank_b)
>         /* The return value of strcmp has opposite meaning.  */
>         return -strcmp (a.c_str (), b.c_str ());
> @@ -528,7 +528,7 @@ riscv_subset_list::add (const char *subset, int 
> major_version,
>      {
>        if (ext->implied_p)
>         {
> -         /* We won't add implied `ext` if it already in list. */
> +         /* We won't add implied `ext` if it is already in list.  */
>           gcc_assert (!implied_p);
>           ext->implied_p = implied_p;
>           ext->major_version = major_version;
> @@ -1150,7 +1150,7 @@ riscv_subset_list::check_conflict_ext ()
>    if (lookup ("zcf") && m_xlen == 64)
>      error_at (*m_loc, "%<-march=%s%>: zcf extension supports in rv32 only",
>               m_arch);
> -
> +
>    if (lookup ("zilsd") && m_xlen == 64)
>      error_at (*m_loc, "%<-march=%s%>: zilsd extension supports in rv32 only",
>               m_arch);
> @@ -2108,7 +2108,7 @@ riscv_compute_multilib (
>      return multilib_dir;
>
>    /* Parsing MULTILIB_SELECT, ignore MULTILIB_REUSE here, we have our own 
> rules.
> -     TODO: most codes are grab from gcc.c, maybe we should refine that?  */
> +     TODO: most code is grabbed from gcc.c, maybe we should refine that?  */
>    p = multilib_select;
>
>    while (*p != '\0')
> diff --git a/gcc/config/riscv/andes-25-series.md 
> b/gcc/config/riscv/andes-25-series.md
> index a649fa48a0b..28ed1ded6ff 100644
> --- a/gcc/config/riscv/andes-25-series.md
> +++ b/gcc/config/riscv/andes-25-series.md
> @@ -184,17 +184,17 @@ (define_insn_reservation "andes_25_vialu" 1
>         (eq_attr "type" "vialu,vicalu,vshift,viminmax,vicmp,vimov,\
>                         vsalu,vaalu,vmov,vector,vimerge"))
>    "andes_25_vpu_pipe + andes_25_vpu_alu")
> -
> +
>  (define_insn_reservation "andes_25_widen_vialu" 2
>    (and (eq_attr "tune" "andes_25_series")
>         (eq_attr "type" "viwalu, vext, vsshift"))
>    "andes_25_vpu_pipe + andes_25_vpu_alu")
> -
> +
>  (define_insn_reservation "andes_25_narrow_vialu" 3
>    (and (eq_attr "tune" "andes_25_series")
>         (eq_attr "type" "vnshift,vnclip"))
>    "andes_25_vpu_pipe + andes_25_vpu_alu")
> -
> +
>  (define_insn_reservation "andes_25_vimul" 2
>    (and (eq_attr "tune" "andes_25_series")
>         (eq_attr "type" "vimul,vimuladd,vsmul"))
> @@ -210,7 +210,7 @@ (define_insn_reservation "andes_25_vperm" 3
>         (eq_attr "type" "vslideup,vslidedown,vislide1up,vislide1down,\
>                         vfslide1up,vfslide1down,vgather"))
>    "andes_25_vpu_pipe + andes_25_vpu_perm")
> -
> +
>  (define_insn_reservation "andes_25_vcompress" 4
>    (and (eq_attr "tune" "andes_25_series")
>         (eq_attr "type" "vcompress"))
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index c86fb16586d..497189cf185 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -684,7 +684,7 @@ (define_insn_and_split 
> "*single_widen_add<any_extend:su><mode>"
>  }
>  [(set_attr "type" "viwalu")])
>
> -;; This combine pattern does not correspond to an single instruction,
> +;; This combine pattern does not correspond to a single instruction,
>  ;; i.e. there is no vwmul.wv instruction. This is a temporary pattern
>  ;; produced by a combine pass and if there is no further combine into
>  ;; vwmul.vv pattern, then fall back to extend pattern and vmul.vv pattern.
> @@ -825,7 +825,7 @@ (define_insn_and_split "*single_widen_first_sub<mode>"
>  }
>  [(set_attr "type" "vector")])
>
> -;; This combine pattern does not correspond to an single instruction,
> +;; This combine pattern does not correspond to a single instruction,
>  ;; i.e. there is no vfwmul.wv instruction. This is a temporary pattern
>  ;; produced by a combine pass and if there is no further combine into
>  ;; vfwmul.vv pattern, then fall back to extend pattern and vfmul.vv pattern.
> @@ -1014,7 +1014,7 @@ (define_insn_and_split "*dual_widen_fmaus<mode>"
>    }
>    [(set_attr "type" "viwmuladd")])
>
> -;; This combine pattern does not correspond to an single instruction.
> +;; This combine pattern does not correspond to a single instruction.
>  ;; This is a temporary pattern produced by a combine pass and if there
>  ;; is no further combine into widen pattern, then fall back to extend
>  ;; pattern and non-widen fma pattern.
> @@ -1067,7 +1067,7 @@ (define_insn_and_split "*dual_widen_fma<mode>"
>    }
>    [(set_attr "type" "vfwmuladd")])
>
> -;; This combine pattern does not correspond to an single instruction.
> +;; This combine pattern does not correspond to a single instruction.
>  ;; This is a temporary pattern produced by a combine pass and if there
>  ;; is no further combine into widen pattern, then fall back to extend
>  ;; pattern and non-widen fma pattern.
> @@ -1119,7 +1119,7 @@ (define_insn_and_split "*dual_widen_fnma<mode>"
>    }
>    [(set_attr "type" "vfwmuladd")])
>
> -;; This combine pattern does not correspond to an single instruction.
> +;; This combine pattern does not correspond to a single instruction.
>  ;; This is a temporary pattern produced by a combine pass and if there
>  ;; is no further combine into widen pattern, then fall back to extend
>  ;; pattern and non-widen fnma pattern.
> @@ -1171,7 +1171,7 @@ (define_insn_and_split "*dual_widen_fms<mode>"
>    }
>    [(set_attr "type" "vfwmuladd")])
>
> -;; This combine pattern does not correspond to an single instruction.
> +;; This combine pattern does not correspond to a single instruction.
>  ;; This is a temporary pattern produced by a combine pass and if there
>  ;; is no further combine into widen pattern, then fall back to extend
>  ;; pattern and non-widen fms pattern.
> @@ -1224,7 +1224,7 @@ (define_insn_and_split "*dual_widen_fnms<mode>"
>    }
>    [(set_attr "type" "vfwmuladd")])
>
> -;; This combine pattern does not correspond to an single instruction.
> +;; This combine pattern does not correspond to a single instruction.
>  ;; This is a temporary pattern produced by a combine pass and if there
>  ;; is no further combine into widen pattern, then fall back to extend
>  ;; pattern and non-widen fnms pattern.
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 2c9dc00f763..c6b823d04a2 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1071,7 +1071,7 @@ (define_insn_and_split "<float_cvt><mode><vnconvert>2"
>  [(set_attr "type" "vfncvtitof")])
>
>  ;; This operation can be performed in the loop vectorizer but unfortunately
> -;; not applicable for now. We can remove this pattern after loop vectorizer
> +;; not applicable for now.  We can remove this pattern after loop vectorizer
>  ;; is able to take care of INT64 to FP16 conversion.
>  (define_expand "<float_cvt><mode><vnnconvert>2"
>    [(set (match_operand:<VNNCONVERT>  0 "register_operand")
> @@ -1369,7 +1369,7 @@ (define_expand "vec_set<mode>"
>     (match_operand           2 "nonmemory_operand")]
>    "TARGET_VECTOR"
>  {
> -  /* If we set the first element, emit an v(f)mv.s.[xf].  */
> +  /* If we set the first element, emit a v(f)mv.s.[xf].  */
>    if (operands[2] == const0_rtx)
>      {
>        rtx ops[] = {operands[0], operands[0], operands[1]};
> diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
> index 980bc4acf58..05559405fcc 100644
> --- a/gcc/config/riscv/bitmanip.md
> +++ b/gcc/config/riscv/bitmanip.md
> @@ -58,7 +58,7 @@ (define_split
>
>  ; Zba does not provide W-forms of sh[123]add(.uw)?, which leads to an
>  ; interesting irregularity: we can generate a signed 32-bit result
> -; using slli(.uw)?+ addw, but a unsigned 32-bit result can be more
> +; using slli(.uw)?+ addw, but an unsigned 32-bit result can be more
>  ; efficiently be generated as sh[123]add+zext.w (the .uw can be
>  ; dropped, if we zero-extend the output anyway).
>  ;
> @@ -1159,7 +1159,7 @@ (define_insn_and_split ""
>     && riscv_const_insns (operands[2], false) != 1
>     /* We need the upper half to be zero.  */
>     && (INTVAL (operands[2]) & HOST_WIDE_INT_C (0xffffffff00000000)) == 0
> -   /* And the the adjusted constant must either be something we can
> +   /* And the adjusted constant must either be something we can
>        implement with andi or bclri.  */
>     && ((SMALL_OPERAND (sext_hwi (INTVAL (operands[2]), 32))
>          || (TARGET_ZBS && popcount_hwi (INTVAL (operands[2])) == 31))
> @@ -1326,7 +1326,7 @@ (define_expand "crc<SUBX1:mode><SUBX:mode>4"
>    DONE;
>  })
>
> -;; If we have an XOR/IOR with a constant operand (C) and the we can
> +;; If we have an XOR/IOR with a constant operand (C) and we can
>  ;; synthesize ~C more efficiently than C, then synthesize ~C and use
>  ;; xnor/orn instead.
>  ;;
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 673b05954e1..1f285a342ba 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -194,7 +194,7 @@ (define_constraint "vp"
>         (match_test "known_eq (rtx_to_poly_int64 (op), 
> BYTES_PER_RISCV_VECTOR)")))
>
>  (define_constraint "vu"
> -  "A undefined vector value."
> +  "An undefined vector value."
>    (and (match_code "unspec")
>         (match_test "XINT (op, 1) == UNSPEC_VUNDEF")))
>
> diff --git a/gcc/config/riscv/gen-riscv-ext-opt.cc 
> b/gcc/config/riscv/gen-riscv-ext-opt.cc
> index 79401fdda42..cc73bd7388a 100644
> --- a/gcc/config/riscv/gen-riscv-ext-opt.cc
> +++ b/gcc/config/riscv/gen-riscv-ext-opt.cc
> @@ -27,7 +27,7 @@ main ()
>    puts ("; License for more details.");
>    puts (";");
>    puts ("; You should have received a copy of the GNU General Public 
> License");
> -  puts ("; along with GCC; see the file COPYING3.  If not see ");
> +  puts ("; along with GCC; see the file COPYING3.  If not see");
>    puts ("; <http://www.gnu.org/licenses/>.");
>
>    puts ("; This file is generated automatically using");
> diff --git a/gcc/config/riscv/gen-riscv-mcpu-texi.cc 
> b/gcc/config/riscv/gen-riscv-mcpu-texi.cc
> index 58845ee1110..b36c3e6245f 100644
> --- a/gcc/config/riscv/gen-riscv-mcpu-texi.cc
> +++ b/gcc/config/riscv/gen-riscv-mcpu-texi.cc
> @@ -20,7 +20,7 @@ main ()
>    puts ("@opindex mcpu");
>    puts ("@item -mcpu=@var{processor-string}");
>    puts ("Use architecture of and optimize the output for the given 
> processor, specified");
> -  puts ("by particular CPU name. Permissible values for this option are:");
> +  puts ("by particular CPU name.  Permissible values for this option are:");
>    puts ("");
>    puts ("");
>
> diff --git a/gcc/config/riscv/generic-vector-ooo.md 
> b/gcc/config/riscv/generic-vector-ooo.md
> index 01bd25816cc..af8c0026d86 100644
> --- a/gcc/config/riscv/generic-vector-ooo.md
> +++ b/gcc/config/riscv/generic-vector-ooo.md
> @@ -17,7 +17,7 @@
>  ;; <http://www.gnu.org/licenses/>.
>  ;; Vector load/store
>
> -;; The insn reservations include "generic" as we won't have a in-order
> +;; The insn reservations include "generic" as we won't have an in-order
>  ;; generic definition for vector instructions.
>
>  (define_automaton "vector_ooo")
> diff --git a/gcc/config/riscv/multilib-generator 
> b/gcc/config/riscv/multilib-generator
> index 52419da7233..d8e56563a5f 100755
> --- a/gcc/config/riscv/multilib-generator
> +++ b/gcc/config/riscv/multilib-generator
> @@ -3,19 +3,19 @@
>  # RISC-V multilib list generator.
>  # Copyright (C) 2011-2026 Free Software Foundation, Inc.
>  # Contributed by Andrew Waterman (and...@sifive.com).
> -#
> +#
>  # This file is part of GCC.
> -#
> +#
>  # GCC is free software; you can redistribute it and/or modify
>  # it under the terms of the GNU General Public License as published by
>  # the Free Software Foundation; either version 3, or (at your option)
>  # any later version.
> -#
> +#
>  # GCC is distributed in the hope that it will be useful,
>  # but WITHOUT ANY WARRANTY; without even the implied warranty of
>  # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>  # GNU General Public License for more details.
> -#
> +#
>  # You should have received a copy of the GNU General Public License
>  # along with GCC; see the file COPYING3.  If not see
>  # <http://www.gnu.org/licenses/>.
> diff --git a/gcc/config/riscv/riscv-avlprop.cc 
> b/gcc/config/riscv/riscv-avlprop.cc
> index d8cbda11cba..a4088e8e51c 100644
> --- a/gcc/config/riscv/riscv-avlprop.cc
> +++ b/gcc/config/riscv/riscv-avlprop.cc
> @@ -6,7 +6,7 @@ This file is part of GCC.
>
>  GCC is free software; you can redistribute it and/or modify
>  it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 3, or(at your option)
> +the Free Software Foundation; either version 3, or (at your option)
>  any later version.
>
>  GCC is distributed in the hope that it will be useful,
> @@ -23,7 +23,7 @@ along with GCC; see the file COPYING3.  If not see
>
>       - Better code maintain:
>         Current LCM-based VSETVL pass is so complicated that codes
> -       there will become even harder to maintain. A straight forward
> +       there will become even harder to maintain.  A straight forward
>         AVL propagation PASS is much easier to maintain.
>
>       - Reduce scalar register pressure:
> @@ -313,13 +313,13 @@ pass_avlprop::get_preferred_avl (
>       - Few code changes in Loop Vectorizer.
>       - Reuse the current clean flow of partial vectorization, That is, apply
>         predicate LEN or MASK into LOAD/STORE operations and other special
> -       arithmetic operations (e.d. DIV), then do the whole vector register
> +       arithmetic operations (e.g., DIV), then do the whole vector register
>         operation if it DON'T affect the correctness.
>         Such flow is used by all other targets like x86, sve, s390, ... etc.
>       - PLUS_EXPR has better gimple optimizations than COND_LEN_ADD.
>
>     We propagate AVL from NON-VLMAX to VLMAX for gimple IR like PLUS_EXPR 
> which
> -   generates the VLMAX instruction due to missed LEN information. The later
> +   generates the VLMAX instruction due to missed LEN information.  The later
>     VSETVL PASS will elided the redundant vsetvls.
>  */
>
> @@ -340,7 +340,7 @@ pass_avlprop::get_vlmax_ta_preferred_avl (insn_info 
> *insn) const
>        const auto *set = dyn_cast<set_info *> (def);
>
>        /* FIXME: Stop AVL propagation if any USE is not a RVV real
> -        instruction. It should be totally enough for vectorized codes since
> +        instruction.  It should be totally enough for vectorized codes since
>          they always locate at extended blocks.
>
>          TODO: We can extend PHI checking for intrinsic codes if it
> diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
> index e3300a14fc0..efdb510ce60 100644
> --- a/gcc/config/riscv/riscv-ext.def
> +++ b/gcc/config/riscv/riscv-ext.def
> @@ -710,7 +710,7 @@ DEFINE_RISCV_EXT(
>        return true;
>      }
>
> -  /* Do nothing for future RV128 specification. Behaviour
> +  /* Do nothing for future RV128 specification.  Behaviour
>       for this case is not yet well defined.  */
>    return false;
>
> diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
> index 7bf3d4effc6..472dabf8a93 100644
> --- a/gcc/config/riscv/riscv-ext.opt
> +++ b/gcc/config/riscv/riscv-ext.opt
> @@ -15,7 +15,7 @@
>  ; License for more details.
>  ;
>  ; You should have received a copy of the GNU General Public License
> -; along with GCC; see the file COPYING3.  If not see
> +; along with GCC; see the file COPYING3.  If not see
>  ; <http://www.gnu.org/licenses/>.
>  ; This file is generated automatically using
>  ;  gcc/config/riscv/gen-riscv-ext-opt.cc from:
> diff --git a/gcc/config/riscv/riscv-modes.def 
> b/gcc/config/riscv/riscv-modes.def
> index c15585b7cfa..29cbf9c057c 100644
> --- a/gcc/config/riscv/riscv-modes.def
> +++ b/gcc/config/riscv/riscv-modes.def
> @@ -29,7 +29,7 @@ ADJUST_FLOAT_FORMAT (BF, &arm_bfloat_half_format);
>
>  /* Vector modes.  */
>
> -/* Encode the ratio of SEW/LMUL into the mask types. There are the following
> +/* Encode the ratio of SEW/LMUL into the mask types.  There are the following
>   * mask types.  */
>
>  /* Encode the ratio of SEW/LMUL into the mask types.
> @@ -342,7 +342,7 @@ RVV_NF4_MODES (4)
>
>  RVV_NF2_MODES (2)
>
> -/* VLS modes used as SIMD auto-vectorization for epilogue. We know the
> +/* VLS modes used as SIMD auto-vectorization for epilogue.  We know the
>     return type of GET_MODE_BITSIZE is poly_uint16 or unsigned short.
>     The maximum bitsize of all vector modes is 65536 = (8192 (LMUL1) * 8),
>     even though RISC-V 'V' ISA spec allow maximum bitsize = 65536 * 8.
> @@ -434,8 +434,8 @@ VLS_MODES (4096); /* V4096QI V2048HI V1024SI V512DI 
> V2048HF V2048BF V1024SF V512
>     be 65536 for a single vector register which means the vector mode in
>     GCC can be maximum = 65536 * 8 bits (LMUL=8).
>     However, 'GET_MODE_SIZE' is using poly_uint16/unsigned short which will
> -   overflow if we specify vector-length = 65536. To support this feature,
> -   we need to change the codes outside the RISC-V port. We will support it in
> +   overflow if we specify vector-length = 65536.  To support this feature,
> +   we need to change the codes outside the RISC-V port.  We will support it 
> in
>     the future.  */
>  #define MAX_BITSIZE_MODE_ANY_MODE (4096 * 8)
>
> diff --git a/gcc/config/riscv/riscv-opt-popretz.cc 
> b/gcc/config/riscv/riscv-opt-popretz.cc
> index f6f26bced2c..a109780417b 100644
> --- a/gcc/config/riscv/riscv-opt-popretz.cc
> +++ b/gcc/config/riscv/riscv-opt-popretz.cc
> @@ -34,7 +34,7 @@
>     Why not use peephole2?
>     ----------------------
>     An alternative approach would be to use a peephole2 pattern to perform 
> this
> -   optimization. However, between "li a0, 0" and "cm.popret", there can be
> +   optimization.  However, between "li a0, 0" and "cm.popret", there can be
>     STACK_TIE and other instructions that make it difficult to write a robust
>     peephole pattern that handles all cases.
>
> @@ -132,7 +132,7 @@ riscv_popret_insn_p (int code)
>
>  /* Convert a cm.popret instruction code to its corresponding cm.popretz code.
>     Given an instruction code for gpr_multi_popret, returns the equivalent
> -   gpr_multi_popretz instruction code. Returns CODE_FOR_nothing if the
> +   gpr_multi_popretz instruction code.  Returns CODE_FOR_nothing if the
>     input is not a valid popret instruction.  */
>  static int
>  riscv_code_for_popretz (int code)
> diff --git a/gcc/config/riscv/riscv-profiles.def 
> b/gcc/config/riscv/riscv-profiles.def
> index 7a5a15b285a..7cd2317fb93 100644
> --- a/gcc/config/riscv/riscv-profiles.def
> +++ b/gcc/config/riscv/riscv-profiles.def
> @@ -17,7 +17,7 @@
>     along with GCC; see the file COPYING3.  If not see
>     <http://www.gnu.org/licenses/>.  */
>
> -/* This is a list of RISC-V Profiles definitions.
> +/* This is a list of RISC-V Profiles definition.
>
>     Before using #include to read this file, define a macro:
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 234d625441d..b0d73f641e1 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -336,10 +336,10 @@ struct cpu_vector_cost
>    /* Cost of a not-taken branch.  */
>    const int cond_not_taken_branch_cost;
>
> -  /* Cost of an VLS modes operations.  */
> +  /* Cost of a VLS modes operations.  */
>    const common_vector_cost *vls;
>
> -  /* Cost of an VLA modes operations.  */
> +  /* Cost of a VLA modes operations.  */
>    const scalable_vector_cost *vla;
>
>    /* Cost of vector register move operations.  */
> @@ -360,7 +360,7 @@ namespace riscv_vector {
>
>  /* These flags describe how to pass the operands to a rvv insn pattern.
>     e.g.:
> -     If a insn has this flags:
> +     If an insn has this flags:
>         HAS_DEST_P | HAS_MASK_P | USE_VUNDEF_MERGE_P
>          | TU_POLICY_P | BINARY_OP_P | FRM_DYN_P
>       that means:
> @@ -373,16 +373,16 @@ namespace riscv_vector {
>         operands[7] is the mask policy operands
>         operands[8] is the rounding mode operands
>
> -     Then you can call `emit_vlmax_insn (flags, icode, ops)` to emit a insn.
> +     Then you can call `emit_vlmax_insn (flags, icode, ops)` to emit an insn.
>       and ops[0] is the dest operand (operands[0]), ops[1] is the mask
>       operand (operands[1]), ops[2] and ops[3] is the two
> -     operands (operands[3], operands[4]) to do the operation. Other operands
> +     operands (operands[3], operands[4]) to do the operation.  Other operands
>       will be created by emit_vlmax_insn according to the flags information.
>  */
>  enum insn_flags : unsigned int
>  {
>    /* flags for dest, mask, merge operands.  */
> -  /* Means INSN has dest operand. False for STORE insn.  */
> +  /* Means INSN has dest operand.  False for STORE insn.  */
>    HAS_DEST_P = 1 << 0,
>    /* Means INSN has mask operand.  */
>    HAS_MASK_P = 1 << 1,
> @@ -510,7 +510,7 @@ enum insn_type : unsigned int
>    BINARY_OP_VXRM_RDN = BINARY_OP | VXRM_RDN_P,
>    BINARY_OP_VXRM_ROD = BINARY_OP | VXRM_ROD_P,
>
> -  /* Ternary operator. Always have real merge operand.  */
> +  /* Ternary operator.  Always have real merge operand.  */
>    TERNARY_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P
>                | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | TERNARY_OP_P,
>    TERNARY_OP_FRM_DYN = TERNARY_OP | FRM_DYN_P,
> diff --git a/gcc/config/riscv/riscv-selftests.cc 
> b/gcc/config/riscv/riscv-selftests.cc
> index d9fd6508254..f151d279e8e 100644
> --- a/gcc/config/riscv/riscv-selftests.cc
> +++ b/gcc/config/riscv/riscv-selftests.cc
> @@ -268,8 +268,8 @@ run_const_vector_selftests (void)
>               emit_move_insn (dest, dup);
>               rtx_insn *insn = get_last_insn ();
>               rtx src = SET_SRC (PATTERN (insn));
> -             /* 1. Should be vmv.v.i for in rang of -16 ~ 15.
> -                2. Should be vmv.v.x for exceed -16 ~ 15.  */
> +             /* 1.  Should be vmv.v.i for in range of -16 ~ 15.
> +                2.  Should be vmv.v.x for exceed -16 ~ 15.  */
>               if (IN_RANGE (val, -16, 15))
>                 ASSERT_TRUE (
>                   rtx_equal_p (XEXP (SET_SRC (PATTERN (insn)), 1), dup));
> diff --git a/gcc/config/riscv/riscv-sr.cc b/gcc/config/riscv/riscv-sr.cc
> index d7fb3c274eb..531ba66cbb1 100644
> --- a/gcc/config/riscv/riscv-sr.cc
> +++ b/gcc/config/riscv/riscv-sr.cc
> @@ -188,7 +188,7 @@ check_for_no_return_call (rtx_insn *prologue)
>       NOTE_INSN_PROLOGUE_END
>       A no-return call instruction
>
> -     If we do, then we can remove the prologue instruction safely. Remember
> +     If we do, then we can remove the prologue instruction safely.  Remember
>       that we've already confirmed by this point that the prologue is a call
>       to riscv_save_0.  */
>
> diff --git a/gcc/config/riscv/riscv-string.cc 
> b/gcc/config/riscv/riscv-string.cc
> index 79e1dd03e5d..7deb0a572de 100644
> --- a/gcc/config/riscv/riscv-string.cc
> +++ b/gcc/config/riscv/riscv-string.cc
> @@ -470,7 +470,7 @@ riscv_expand_strcmp_scalar (rtx result, rtx src1, rtx 
> src2,
>     The result will be stored in RESULT.
>     The strings are referenced by SRC1 and SRC2.
>     The argument BYTES_RTX either holds the number of characters to
> -   compare, or is NULL_RTX. The argument ALIGN_RTX holds the alignment.
> +   compare, or is NULL_RTX.  The argument ALIGN_RTX holds the alignment.
>
>     Return true if expansion was successful, or false otherwise.  */
>
> @@ -707,7 +707,7 @@ emit_memcmp_scalar_result_calculation (rtx result, rtx 
> data1, rtx data2)
>    do_ior3 (result, result, const1_rtx);
>  }
>
> -/* Expand memcmp using scalar instructions (incl. Zbb).
> +/* Expand memcmp using scalar instructions (including Zbb).
>
>     RESULT is the register where the return value will be stored.
>     The source pointers are SRC1 and SRC2 (NBYTES bytes to compare).  */
> diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
> index 460093d953a..2f7d943613f 100644
> --- a/gcc/config/riscv/riscv-subset.h
> +++ b/gcc/config/riscv/riscv-subset.h
> @@ -45,7 +45,7 @@ class riscv_subset_list
>  {
>  public:
>    /* Because the parse method is called in several places, to prevent 
> repeated
> -     errors, use this flag to prevent it from repeating parse. */
> +     errors, use this flag to prevent it from repeating the parse.  */
>    static bool parse_failed;
>
>  private:
> diff --git a/gcc/config/riscv/riscv-target-attr.cc 
> b/gcc/config/riscv/riscv-target-attr.cc
> index 3628dbb9b1b..5f265d0b242 100644
> --- a/gcc/config/riscv/riscv-target-attr.cc
> +++ b/gcc/config/riscv/riscv-target-attr.cc
> @@ -479,8 +479,8 @@ riscv_process_target_attr (tree args,
>
>  /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P.
>     This is used to process attribute ((target ("..."))).
> -   Note, that riscv_set_current_function() has not been called before,
> -   so we need must not mess with the current global_options, which
> +   Note that riscv_set_current_function () has not been called before,
> +   so we must not mess with the current global_options, which
>     likely belong to another function.  */
>
>  bool
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index b0d2a1b966c..b7dd1c8279a 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -97,7 +97,7 @@ is_vlmax_len_p (machine_mode mode, rtx len)
>
>  /* Helper functions for insn_flags && insn_types */
>
> -/* Return true if caller need pass mask operand for insn pattern with
> +/* Return true if caller needs to pass mask operand for insn pattern with
>     INSN_FLAGS. */
>
>  static bool
> @@ -304,7 +304,7 @@ public:
>         machine_mode mode = insn_data[(int) icode].operand[m_opno].mode;
>         /* 'create_input_operand doesn't allow VOIDmode.
>            According to vector.md, we may have some patterns that do not have
> -          explicit machine mode specifying the operand. Such operands are
> +          explicit machine mode specifying the operand.  Such operands are
>            always Pmode.  */
>         if (mode == VOIDmode)
>           mode = Pmode;
> @@ -406,9 +406,9 @@ private:
>     vector mode.  For VLA modes this corresponds to VLMAX.
>
>     Unless the vector length can be encoded in the vsetivl[i] instruction this
> -   function must only be used as long as we can create pseudo registers. 
> This is
> -   because it will set a pseudo register to VLMAX using vsetvl and use this 
> as
> -   definition for the vector length.  */
> +   function must only be used as long as we can create pseudo registers.  
> This
> +   is because it will set a pseudo register to VLMAX using vsetvl and use 
> this
> +   as definition for the vector length.  */
>  void
>  emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops)
>  {
> @@ -702,7 +702,7 @@ rvv_builder::single_step_npatterns_p () const
>  }
>
>  /* Return true if the diff between const vector and vid sequence
> -   is repeated. For example as below cases:
> +   is repeated.  For example as below cases:
>     The diff means the const vector - vid.
>       CASE 1:
>       CONST VECTOR: {3, 2, 1, 0, 7, 6, 5, 4, ... }
> @@ -928,8 +928,8 @@ autovec_use_vlmax_p (void)
>           || rvv_vector_bits == RVV_VECTOR_BITS_ZVL;
>  }
>
> -/* This function emits VLMAX vrgather instruction. Emit vrgather.vx/vi when 
> sel
> -   is a const duplicate vector. Otherwise, emit vrgather.vv.  */
> +/* This function emits VLMAX vrgather instruction.  Emit vrgather.vx/vi when 
> sel
> +   is a const duplicate vector.  Otherwise, emit vrgather.vv.  */
>  static void
>  emit_vlmax_gather_insn (rtx target, rtx op, rtx sel)
>  {
> @@ -2070,8 +2070,8 @@ get_nf (machine_mode mode)
>    return mode_vtype_infos.nf[mode];
>  }
>
> -/* Return the subpart mode of the tuple mode. For RVVM2x2SImode,
> -   the subpart mode is RVVM2SImode. This will help to build
> +/* Return the subpart mode of the tuple mode.  For RVVM2x2SImode,
> +   the subpart mode is RVVM2SImode.  This will help to build
>     array/struct type in builtins.  */
>  machine_mode
>  get_subpart_mode (machine_mode mode)
> @@ -2131,7 +2131,7 @@ get_ma (rtx ma)
>    return INTVAL (ma);
>  }
>
> -/* Get prefer tail policy.  */
> +/* Get preferred tail policy.  */
>  enum tail_policy
>  get_prefer_tail_policy ()
>  {
> @@ -2140,7 +2140,7 @@ get_prefer_tail_policy ()
>    return TAIL_ANY;
>  }
>
> -/* Get prefer mask policy.  */
> +/* Get preferred mask policy.  */
>  enum mask_policy
>  get_prefer_mask_policy ()
>  {
> @@ -2936,7 +2936,7 @@ expand_vec_init (rtx target, rtx vals)
>    /* Optimize trailing same elements sequence:
>        v = {y, y2, y3, y4, y5, x, x, x, x, x, x, x, x, x, x, x};  */
>    if (!expand_vector_init_trailing_same_elem (target, v, nelts))
> -    /* Handle common situation by vslide1down. This function can handle any
> +    /* Handle common situation by vslide1down.  This function can handle any
>         situation of vec_init<mode>. Only the cases that are not optimized 
> above
>         will fall through here.  */
>      expand_vector_init_insert_elems (target, v, nelts);
> @@ -3298,9 +3298,9 @@ expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
>    machine_mode sel_mode = GET_MODE (sel);
>    poly_uint64 nunits = GET_MODE_NUNITS (sel_mode);
>
> -  /* Check if the sel only references the first values vector. If each select
> +  /* Check if the sel only references the first values vector.  If each 
> select
>       index is in range of [0, nunits - 1]. A single vrgather instructions is
> -     enough. Since we will use vrgatherei16.vv for variable-length vector,
> +     enough.  Since we will use vrgatherei16.vv for variable-length vector,
>       it is never out of range and we don't need to modulo the index.  */
>    if (nunits.is_constant () && const_vec_all_in_range_p (sel, 0, nunits - 1))
>      {
> @@ -3418,7 +3418,7 @@ get_gather_index_mode (struct expand_vec_perm_d *d)
>  }
>
>  /* Recognize the patterns that we can use merge operation to shuffle the
> -   vectors. The value of Each element (index i) in selector can only be
> +   vectors.  The value of Each element (index i) in selector can only be
>     either i or nunits + i.  We will check the pattern is actually monotonic.
>
>     E.g.
> @@ -3615,7 +3615,7 @@ shuffle_consecutive_patterns (struct expand_vec_perm_d 
> *d)
>  }
>
>  /* Recognize the patterns that we can use compress operation to shuffle the
> -   vectors. The perm selector of compress pattern is divided into 2 part:
> +   vectors.  The perm selector of compress pattern is divided into 2 part:
>     The first part is the random index number < NUNITS.
>     The second part is consecutive last N index number >= NUNITS.
>
> @@ -4156,7 +4156,7 @@ shuffle_bswap_pattern (struct expand_vec_perm_d *d)
>      case 32:
>      case 64:
>        /* We will have VEC_PERM_EXPR after rtl expand when invoking
> -        __builtin_bswap. It will generate about 9 instructions in
> +        __builtin_bswap.  It will generate about 9 instructions in
>          loop as below, no matter it is bswap16, bswap32 or bswap64.
>            .L2:
>          1 vle16.v v4,0(a0)
> @@ -4170,7 +4170,7 @@ shuffle_bswap_pattern (struct expand_vec_perm_d *d)
>          9 add     a3,a3,a2
>            bne     a4,zero,.L2
>
> -        But for bswap16 we may have a even simple code gen, which
> +        But for bswap16 we may have an even simple code gen, which
>          has only 7 instructions in loop as below.
>            .L5
>          1 vle8.v  v2,0(a5)
> @@ -4483,7 +4483,7 @@ expand_vec_perm_const (machine_mode vmode, machine_mode 
> op_mode, rtx target,
>                        rtx op0, rtx op1, const vec_perm_indices &sel)
>  {
>    /* RVV doesn't have Mask type pack/unpack instructions and we don't use
> -     mask to do the iteration loop control. Just disable it directly.  */
> +     mask to do the iteration loop control.  Just disable it directly.  */
>    if (GET_MODE_CLASS (vmode) == MODE_VECTOR_BOOL)
>      return false;
>
> @@ -4543,7 +4543,7 @@ expand_select_vl (rtx *ops)
>        return;
>      }
>    /* We arbitrary picked QImode as inner scalar mode to get vector mode.
> -     since vsetvl only demand ratio. We let VSETVL PASS to optimize it.  */
> +     since vsetvl only demand ratio.  We let VSETVL PASS to optimize it.  */
>    scalar_int_mode mode = QImode;
>    machine_mode rvv_mode = get_vector_mode (mode, nunits).require ();
>    emit_insn (gen_no_side_effects_vsetvl_rtx (rvv_mode, ops[0], ops[1]));
> @@ -5203,7 +5203,7 @@ cmp_lmul_gt_one (machine_mode mode)
>    return false;
>  }
>
> -/* Return true if the VLS mode is legal. There are 2 cases here.
> +/* Return true if the VLS mode is legal.  There are 2 cases here.
>
>     1. Enable VLS modes for VLA vectorization since fixed length VLMAX mode
>        is the highest priority choice and should not conflict with VLS modes.
> @@ -5753,8 +5753,8 @@ expand_vec_ssadd (rtx op_0, rtx op_1, rtx op_2, 
> machine_mode vec_mode)
>    emit_vec_binary_alu (op_0, op_1, op_2, SS_PLUS, vec_mode);
>  }
>
> -/* Expand the standard name usadd<mode>3 for vector mode,  we can leverage
> -   the vector fixed point vector single-width saturating add directly.  */
> +/* Expand the standard name ussub<mode>3 for vector mode,  we can leverage
> +   the vector fixed point vector single-width saturating subtract directly.  
> */
>
>  void
>  expand_vec_ussub (rtx op_0, rtx op_1, rtx op_2, machine_mode vec_mode)
> @@ -5803,7 +5803,7 @@ expand_vec_double_sstrunc (rtx op_0, rtx op_1, 
> machine_mode vec_mode)
>    emit_vlmax_insn (icode, BINARY_OP_VXRM_RNU, ops);
>  }
>
> -/* Expand the standard name ustrunc<m><n>2 for double vector mode,  like
> +/* Expand the standard name ustrunc<m><n>2 for quad vector mode,  like
>     DI => HI.  we can leverage the vector fixed point vector narrowing
>     fixed-point clip directly.  */
>
> @@ -6142,7 +6142,7 @@ vlmax_avl_type_p (rtx_insn *rinsn)
>    return INTVAL (avl_type) == VLMAX;
>  }
>
> -/* Return true if it is an RVV instruction depends on VL global
> +/* Return true if it is an RVV instruction that depends on VL global
>     status register.  */
>  bool
>  has_vl_op (rtx_insn *rinsn)
> @@ -6154,8 +6154,9 @@ has_vl_op (rtx_insn *rinsn)
>  static bool
>  get_default_ta ()
>  {
> -  /* For the instruction that doesn't require TA, we still need a default 
> value
> -     to emit vsetvl. We pick up the default value according to prefer 
> policy. */
> +  /* For the instruction that does not require TA, we still need a default
> +     value to emit vsetvl.  We pick up the default value according to
> +     preferred policy.  */
>    return (bool) (get_prefer_tail_policy () & 0x1
>                  || (get_prefer_tail_policy () >> 1 & 0x1));
>  }
> @@ -6200,7 +6201,7 @@ vlmax_avl_p (rtx x)
>    return x && rtx_equal_p (x, RVV_VLMAX);
>  }
>
> -/* Helper function to get SEW operand. We always have SEW value for
> +/* Helper function to get SEW operand.  We always have SEW value for
>     all RVV instructions that have VTYPE OP.  */
>  uint8_t
>  get_sew (rtx_insn *rinsn)
> @@ -6208,7 +6209,7 @@ get_sew (rtx_insn *rinsn)
>    return get_attr_sew (rinsn);
>  }
>
> -/* Helper function to get VLMUL operand. We always have VLMUL value for
> +/* Helper function to get VLMUL operand.  We always have VLMUL value for
>     all RVV instructions that have VTYPE OP. */
>  enum vlmul_type
>  get_vlmul (rtx_insn *rinsn)
> diff --git a/gcc/config/riscv/riscv-vect-permconst.cc 
> b/gcc/config/riscv/riscv-vect-permconst.cc
> index 34a4a9b97f4..9692b47960b 100644
> --- a/gcc/config/riscv/riscv-vect-permconst.cc
> +++ b/gcc/config/riscv/riscv-vect-permconst.cc
> @@ -4,7 +4,7 @@ This file is part of GCC.
>
>  GCC is free software; you can redistribute it and/or modify
>  it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 3, or(at your option)
> +the Free Software Foundation; either version 3, or (at your option)
>  any later version.
>
>  GCC is distributed in the hope that it will be useful,
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 525a622882a..8f39a28856c 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -90,7 +90,7 @@ public:
>        }
>      else
>        {
> -       /* Normalize same RATO (SEW/LMUL) into same vsetvl instruction.
> +       /* Normalize same RATIO (SEW/LMUL) into same vsetvl instruction.
>
>              - e8,mf8/e16,mf4/e32,mf2/e64,m1 --> e8mf8
>              - e8,mf4/e16,mf2/e32,m1/e64,m2  --> e8mf4
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def 
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 3ae3de80897..f64d42d1823 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -11,11 +11,11 @@ any later version.
>
>  GCC is distributed in the hope that it will be useful,
>  but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>  GNU General Public License for more details.
>
>  You should have received a copy of the GNU General Public License
> -along with GCC; see the file COPYING3. If not see
> +along with GCC; see the file COPYING3.  If not see
>  <http://www.gnu.org/licenses/>. */
>
>  /* Use "DEF_RVV_FUNCTION" macro to define RVV intrinsic functions.
> @@ -106,7 +106,7 @@ DEF_RVV_FUNCTION (vlenb, vlenb, none_preds, 
> ul_none_void_ops)
>  DEF_RVV_FUNCTION (vsetvl, vsetvl, none_preds, i_none_size_size_ops)
>  DEF_RVV_FUNCTION (vsetvlmax, vsetvlmax, none_preds, i_none_size_void_ops)
>
> -/* 7. Vector Loads and Stores. */
> +/* 7.  Vector Loads and Stores.  */
>
>  // 7.4. Vector Unit-Stride Instructions
>  DEF_RVV_FUNCTION (vle, loadstore, full_preds, all_v_scalar_const_ptr_ops)
> @@ -299,7 +299,7 @@ DEF_RVV_FUNCTION (vmerge, no_mask_policy, none_tu_preds, 
> iu_vvxm_ops)
>  DEF_RVV_FUNCTION (vmv_v, move, none_tu_preds, all_v_ops)
>  DEF_RVV_FUNCTION (vmv_v, move, none_tu_preds, iu_x_ops)
>
> -/* 12. Vector Fixed-Point Arithmetic Instructions. */
> +/* 12.  Vector Fixed-Point Arithmetic Instructions.  */
>
>  // 12.1. Vector Single-Width Saturating Add and Subtract
>  DEF_RVV_FUNCTION (vsaddu, alu, full_preds, u_vvv_ops)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc 
> b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> index 3bf40c432c2..a113bae56e1 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> @@ -105,7 +105,7 @@ supports_vectype_p (const function_group_info &group, 
> unsigned int vec_type_idx)
>  /* Add a function instance for every operand && predicate && args
>     combination in GROUP.  Take the function base name from GROUP && operand
>     suffix from operand_suffixes && mode suffix from type_suffixes && 
> predication
> -   suffix from predication_suffixes. Use apply_predication to add in
> +   suffix from predication_suffixes.  Use apply_predication to add in
>     the predicate.  */
>  static void
>  build_all (function_builder &b, const function_group_info &group)
> @@ -608,7 +608,7 @@ struct reduc_alu_frm_def : public build_frm_base
>    }
>  };
>
> -/* widen_alu_def class. Handle vwadd/vwsub. Unlike
> +/* widen_alu_def class.  Handle vwadd/vwsub.  Unlike
>     vadd.vx/vadd.vv/vwmul.vv/vwmul.vx, vwadd.vv/vwadd.vx/vwadd.wv/vwadd.wx has
>     'OP' suffix in overloaded API.  */
>  struct widen_alu_def : public build_base
> @@ -634,7 +634,7 @@ struct widen_alu_def : public build_base
>    }
>  };
>
> -/* no_mask_policy_def class. Such instructions belong to this class
> +/* no_mask_policy_def class.  Such instructions belong to this class
>     doesn't need mask policy.  */
>  struct no_mask_policy_def : public build_base
>  {
> @@ -655,7 +655,7 @@ struct no_mask_policy_def : public build_base
>    }
>  };
>
> -/* return_mask_def class. Such instructions belong to this class
> +/* return_mask_def class.  Such instructions belong to this class
>     is returning mask value.  */
>  struct return_mask_def : public build_base
>  {
> @@ -683,7 +683,7 @@ struct return_mask_def : public build_base
>    }
>  };
>
> -/* narrow_alu_def class. Handle narrowing instructions like vnsrl.wv.  */
> +/* narrow_alu_def class.  Handle narrowing instructions like vnsrl.wv.  */
>  struct narrow_alu_def : public build_base
>  {
>    char *get_name (function_builder &b, const function_instance &instance,
> @@ -726,7 +726,7 @@ struct narrow_alu_def : public build_base
>    }
>  };
>
> -/* move_def class. Handle vmv.v.v/vmv.v.x.  */
> +/* move_def class.  Handle vmv.v.v/vmv.v.x.  */
>  struct move_def : public build_base
>  {
>    char *get_name (function_builder &b, const function_instance &instance,
> @@ -1320,7 +1320,7 @@ struct sf_vqmacc_def : public build_base
>    }
>  };
>
> -/* sf_vfnrclip_def class. Handle instructions like vfnrclip.  */
> +/* sf_vfnrclip_def class.  Handle instructions like vfnrclip.  */
>  struct sf_vfnrclip_def : public build_base
>  {
>    char *get_name (function_builder &b, const function_instance &instance,
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 56f55109188..fd64771de9e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -11,11 +11,11 @@ any later version.
>
>  GCC is distributed in the hope that it will be useful,
>  but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>  GNU General Public License for more details.
>
>  You should have received a copy of the GNU General Public License
> -along with GCC; see the file COPYING3. If not see
> +along with GCC; see the file COPYING3.  If not see
>  <http://www.gnu.org/licenses/>. */
>
>  /* Use "DEF_RVV_I_OPS" macro include all signed integer which will be
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 9e9e56b2f60..b8be45ed942 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -62,10 +62,10 @@ namespace riscv_vector {
>  struct vector_type_info
>  {
>    /* The name of the type as declared by riscv_vector.h
> -     which is recommend to use. For example: 'vint32m1_t'.  */
> +     which is recommended to use.  For example: 'vint32m1_t'.  */
>    const char *name;
>
> -  /* ABI name of vector type. The type is always available
> +  /* ABI name of vector type.  The type is always available
>       under this name, even when riscv_vector.h isn't included.
>       For example:  '__rvv_int32m1_t'.  */
>    const char *abi_name;
> @@ -84,25 +84,25 @@ public:
>    tree GTY ((skip)) decl;
>
>    /* The overload hash of non-overloaded intrinsic is determined by
> -     the overload name and argument list. Adding the overload name to
> +     the overload name and argument list.  Adding the overload name to
>       the hash is also to address the following situations:
>       vint16mf4_t  __riscv_vreinterpret_i16mf4 (vfloat16mf4_t src);
>       vuint16mf4_t __riscv_vreinterpret_u16mf4 (vfloat16mf4_t src);
>       The base, shape and argument list of the vreinterpret instance are
> -     the same, only the overload name is different. Therefore, it is
> -     enough to add overload_name and argument list to the hash value.*/
> +     the same, only the overload name is different.  Therefore, it is
> +     enough to add overload_name and argument list to the hash value.  */
>    const char *overload_name;
>
> -  /* The argument list part of the hash value. Add the unsigned/signed type
> -     and machine mode of each argument to the hash value. */
> +  /* The argument list part of the hash value.  Add the unsigned/signed type
> +     and machine mode of each argument to the hash value.  */
>    vec<tree> GTY ((skip)) argument_types;
>
>    /* True if the decl represents an overloaded function that needs to be
> -     resolved. */
> +     resolved.  */
>    bool overloaded_p;
>
> -  /* The hash value to indicate the non-overloaded function. Generate hash 
> value
> -     based on overload_name and argument_types. */
> +  /* The hash value to indicate the non-overloaded function.  Generate hash
> +     value based on overload_name and argument_types.  */
>    hashval_t overloaded_hash () const;
>
>    /* Generate hash value based on the overload_name and the argument list 
> passed
> @@ -3699,7 +3699,7 @@ struct pragma_intrinsic_flags
>  static void
>  riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags)
>  {
> -  /* We already defer the required extension checking to expantion time, so 
> we
> +  /* We already defer the required extension checking to expansion time, so 
> we
>       only need to pollute those flags that might affect the type 
> registration.
>
>       e.g. zvfbmin and zvfhmin are required to define the vector bf16 and f16,
> @@ -3754,10 +3754,10 @@ riscv_pragma_intrinsic_flags_restore (struct 
> pragma_intrinsic_flags *flags)
>  /* RAII class for enabling enough RVV features to define the built-in
>     types and implement the riscv_vector.h pragma.
>
> -   Note: According to 'TYPE_MODE' macro implementation, we need set
> +   Note: According to 'TYPE_MODE' macro implementation, we need to set
>     have_regs_of_mode[mode] to be true if we want to get the exact mode
> -   from 'TYPE_MODE'. However, have_regs_of_mode has not been set yet in
> -   targetm.init_builtins (). We need rvv_switcher to set have_regs_of_mode
> +   from 'TYPE_MODE'.  However, have_regs_of_mode has not been set yet in
> +   targetm.init_builtins ().  We need rvv_switcher to set have_regs_of_mode
>     before targetm.init_builtins () and recover back have_regs_of_mode
>     after targetm.init_builtins ().  */
>  class rvv_switcher
> @@ -3884,7 +3884,7 @@ register_builtin_type (vector_type_index type, tree 
> eltype, machine_mode mode)
>    builtin_types[type].scalar_const_ptr = build_const_pointer (eltype);
>    /* TODO: We currently just skip the register of the illegal RVV type.
>       Ideally, we should report error message more friendly instead of
> -     reporting "unknown" type. Support more friendly error message in
> +     reporting "unknown" type.  Support more friendly error message in
>       the future.  */
>    if (!riscv_vla_mode_p (mode))
>      return;
> @@ -3912,7 +3912,7 @@ register_tuple_type (vector_type_index type, 
> vector_type_index subpart_type,
>  {
>    /* TODO: We currently just skip the register of the illegal RVV type.
>      Ideally, we should report error message more friendly instead of
> -    reporting "unknown" type. Support more friendly error message in
> +    reporting "unknown" type.  Support more friendly error message in
>      the future.  */
>    if (!abi_vector_types[subpart_type])
>      return;
> @@ -4024,7 +4024,7 @@ register_vector_type (vector_type_index type)
>       is disabled according to '-march'.  */
>    /* TODO: We currently just skip the register of the illegal RVV type.
>       Ideally, we should report error message more friendly instead of
> -     reporting "unknown" type. Support more friendly error message in
> +     reporting "unknown" type.  Support more friendly error message in
>       the future.  */
>    if (!vectype)
>      return;
> @@ -4095,7 +4095,7 @@ required_extensions_p (enum rvv_base_type type)
>
>  /* Check whether all the RVV_REQUIRE_* values in REQUIRED_EXTENSIONS are
>     enabled.
> -   TODO: We defer the required extensions to expantion time, this function is
> +   TODO: We defer the required extensions to expansion time, this function is
>          only doing the legality now, and we may rename this function and 
> moving
>          to another layer.  */
>  static bool
> @@ -4141,8 +4141,8 @@ use_real_merge_p (enum predication_type_index pred)
>          || pred == PRED_TYPE_mu;
>  }
>
> -/* Get TAIL policy for predication. If predication indicates TU, return the 
> TU.
> -   Otherwise, return the prefer default configuration.  */
> +/* Get TAIL policy for predication.  If predication indicates TU, return the 
> TU.
> +   Otherwise, return the preferred default configuration.  */
>  static rtx
>  get_tail_policy_for_pred (enum predication_type_index pred)
>  {
> @@ -4151,8 +4151,8 @@ get_tail_policy_for_pred (enum predication_type_index 
> pred)
>    return gen_int_mode (get_prefer_tail_policy (), Pmode);
>  }
>
> -/* Get MASK policy for predication. If predication indicates MU, return the 
> MU.
> -   Otherwise, return the prefer default configuration.  */
> +/* Get MASK policy for predication.  If predication indicates MU, return the 
> MU.
> +   Otherwise, return the preferred default configuration.  */
>  static rtx
>  get_mask_policy_for_pred (enum predication_type_index pred)
>  {
> @@ -4227,8 +4227,8 @@ tree
>  rvv_arg_type_info::get_tree_type (vector_type_index type_idx) const
>  {
>    /* If the builtin type is not registered means '-march' doesn't
> -     satisfy the require extension of the type. For example,
> -     vfloat32m1_t require floating-point extension. In this case,
> +     satisfy the require extension of the type.  For example,
> +     vfloat32m1_t require floating-point extension.  In this case,
>       just return NULL_TREE.  */
>    if (type_idx != VECTOR_TYPE_INVALID && !builtin_types[type_idx].vector)
>      return NULL_TREE;
> @@ -4580,11 +4580,11 @@ function_builder::add_function (const 
> function_instance &instance,
>
>       Currently, tree-streamer-in.c:unpack_ts_function_decl_value_fields
>       validates that tree nodes returned by TARGET_BUILTIN_DECL are non-NULL 
> and
> -     some node other than error_mark_node. This is a holdover from when 
> builtin
> +     some node other than error_mark_node.  This is a holdover from when 
> builtin
>       decls were streamed by code rather than by value.
>
>       Ultimately, we should be able to remove this validation of BUILT_IN_MD
> -     nodes and remove the target hook. For now, however, we need to appease 
> the
> +     nodes and remove the target hook.  For now, however, we need to appease 
> the
>       validation and return a non-NULL, non-error_mark_node node, so we
>       arbitrarily choose integer_zero_node.  */
>    tree decl = in_lto_p
> @@ -4612,9 +4612,9 @@ function_builder::add_function (const function_instance 
> &instance,
>  }
>
>  /* Add a built-in function for INSTANCE, with the argument types given
> -   by ARGUMENT_TYPES and the return type given by RETURN_TYPE. NAME is
> -   the "full" name for C function. OVERLOAD_NAME is the "short" name for
> -   C++ overloaded function. OVERLOAD_NAME can be nullptr because some
> +   by ARGUMENT_TYPES and the return type given by RETURN_TYPE.  NAME is
> +   the "full" name for C function.  OVERLOAD_NAME is the "short" name for
> +   C++ overloaded function.  OVERLOAD_NAME can be nullptr because some
>     instance doesn't have C++ overloaded function.  */
>  void
>  function_builder::add_unique_function (const function_instance &instance,
> @@ -4757,8 +4757,8 @@ function_expander::add_input_operand (unsigned argno)
>    add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x);
>  }
>
> -/* Since we may normalize vop/vop_tu/vop_m/vop_tumu.. into a single patter.
> -   We add a undef for the intrinsics that don't need a real merge.  */
> +/* Since we may normalize vop/vop_tu/vop_m/vop_tumu.. into a single pattern.
> +   We add an undef for the intrinsics that don't need a real merge.  */
>  void
>  function_expander::add_vundef_operand (machine_mode mode)
>  {
> diff --git a/gcc/config/riscv/riscv-vector-builtins.def 
> b/gcc/config/riscv/riscv-vector-builtins.def
> index 01e7409f5dc..e4e23ce32b2 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -19,22 +19,22 @@ along with GCC; see the file COPYING3.  If not see
>  <http://www.gnu.org/licenses/>.  */
>
>  /* Use "DEF_RVV_TYPE" macro to define RVV datatype builtins.
> -   1.The 'NAME' argument is the name exposed to users.
> +   1.  The 'NAME' argument is the name exposed to users.
>       For example, "vint32m1_t".
> -   2.The 'NCHARS' argument is the length of ABI-name.
> +   2.  The 'NCHARS' argument is the length of ABI-name.
>       For example, length of "__rvv_int32m1_t" is 15.
> -   3.The 'ABI_NAME' argument is the ABI-name. For example, "__rvv_int32m1_t".
> -   4.The 'SCALAR_TYPE' argument is associated scalar type which is used in
> -     "build_vector_type_for_mode". For "vint32m1_t", we use 
> "intSI_type_node" in
> -     RV64. Otherwise, we use "long_integer_type_node".
> -   5.The 'VECTOR_MODE' is the machine modes of corresponding RVV type used
> +   3.  The 'ABI_NAME' argument is the ABI-name.  For example, 
> "__rvv_int32m1_t".
> +   4.  The 'SCALAR_TYPE' argument is associated scalar type which is used in
> +     "build_vector_type_for_mode".  For "vint32m1_t", we use 
> "intSI_type_node"
> +     in RV64.  Otherwise, we use "long_integer_type_node".
> +   5.  The 'VECTOR_MODE' is the machine modes of corresponding RVV type used
>       in "build_vector_type_for_mode".
>       For example: VECTOR_MODE = RVVM1SImode for "vint32m1_t".
> -   6.The 'VECTOR_SUFFIX' define mode suffix for vector type.
> +   6.  The 'VECTOR_SUFFIX' define mode suffix for vector type.
>       For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vector = i32m1.
> -   7.The 'SCALAR_SUFFIX' define mode suffix for scalar type.
> +   7.  The 'SCALAR_SUFFIX' define mode suffix for scalar type.
>       For example: type_suffixes[VECTOR_TYPE_vin32m1_t].scalar = i32.
> -   8.The 'VSETVL_SUFFIX' define mode suffix for vsetvli instruction.
> +   8.  The 'VSETVL_SUFFIX' define mode suffix for vsetvli instruction.
>       For example: type_suffixes[VECTOR_TYPE_vin32m1_t].vsetvl = e32m1.
>  */
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.h 
> b/gcc/config/riscv/riscv-vector-builtins.h
> index d5fe0cd7a22..8d6473f4837 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.h
> +++ b/gcc/config/riscv/riscv-vector-builtins.h
> @@ -46,7 +46,7 @@
>     predication suffix stay the same.
>
>     - The function_instance class describes contains all properties of each
> -     individual function. Such these information will be used by
> +     individual function.  Such these information will be used by
>       function_builder, function_base, function_shape, gimple_folder,
>       function_expander, etc.
>
> @@ -414,7 +414,7 @@ struct function_group_info
>       The function supports every combination of the two.
>       The list of predication is terminated by two NUM_PRED_TYPES,
>       while the list of operand info is terminated by NUM_BASE_TYPES.
> -     The list of these type suffix is lexicographically ordered based
> +     The list of these type suffixes is lexicographically ordered based
>       on the index value.  */
>    const predication_type_index *preds;
>    const rvv_op_info ops_infos;
> @@ -732,7 +732,7 @@ function_expander::add_output_operand (machine_mode mode, 
> rtx target)
>    create_output_operand (&m_ops[opno++], target, mode);
>  }
>
> -/* Since we may normalize vop/vop_tu/vop_m/vop_tumu.. into a single patter.
> +/* Since we may normalize vop/vop_tu/vop_m/vop_tumu.. into a single pattern.
>     We add a fake all true mask for the intrinsics that don't need a real 
> mask.
>   */
>  inline void
> @@ -860,7 +860,7 @@ function_base::has_merge_operand_p () const
>    return true;
>  }
>
> -/* We choose to return false by default since most of the intrinsics does
> +/* We choose to return false by default since most of the intrinsics do
>     not have rounding mode operand.  */
>  inline bool
>  function_base::has_rounding_mode_operand_p () const
> @@ -868,7 +868,7 @@ function_base::has_rounding_mode_operand_p () const
>    return false;
>  }
>
> -/* We choose to return false by default since most of the intrinsics does
> +/* We choose to return false by default since most of the intrinsics do
>     not need frm operand.  */
>  inline bool
>  function_base::may_require_frm_p () const
> @@ -876,7 +876,7 @@ function_base::may_require_frm_p () const
>    return false;
>  }
>
> -/* We choose to return false by default since most of the intrinsics does
> +/* We choose to return false by default since most of the intrinsics do
>     not need vxrm operand.  */
>  inline bool
>  function_base::may_require_vxrm_p () const
> diff --git a/gcc/config/riscv/riscv-vector-costs.cc 
> b/gcc/config/riscv/riscv-vector-costs.cc
> index 8e602752664..bfb8a0ca63b 100644
> --- a/gcc/config/riscv/riscv-vector-costs.cc
> +++ b/gcc/config/riscv/riscv-vector-costs.cc
> @@ -515,7 +515,7 @@ compute_nregs_for_mode (loop_vec_info loop_vinfo, 
> machine_mode mode,
>  }
>
>  /* This function helps to determine whether current LMUL will cause
> -   potential vector register (V_REG) spillings according to live range
> +   potential vector register (V_REG) spilling according to live range
>     information.
>
>       - First, compute how many variable are alive of each program point
> @@ -965,7 +965,7 @@ costs::has_unexpected_spills_p (loop_vec_info loop_vinfo)
>             = (*program_points_per_bb.get (bb)).length () + 1;
>           if ((*iter).second.is_empty ())
>             continue;
> -         /* We prefer larger LMUL unless it causes register spillings.  */
> +         /* We prefer larger LMUL unless it causes register spilling.  */
>           unsigned int nregs
>             = max_number_of_live_regs (loop_vinfo, bb, (*iter).second,
>                                        max_point, biggest_mode, lmul);
> diff --git a/gcc/config/riscv/riscv-vector-costs.h 
> b/gcc/config/riscv/riscv-vector-costs.h
> index 9a620b71938..74f1eab4001 100644
> --- a/gcc/config/riscv/riscv-vector-costs.h
> +++ b/gcc/config/riscv/riscv-vector-costs.h
> @@ -71,7 +71,7 @@ private:
>
>    /* On some CPUs, VLA and VLS provide the same theoretical vector
>       throughput, such as 4x128 VLS vs. 2x256 VLA.  In those
> -     situations, we try to predict whether an VLS implementation
> +     situations, we try to predict whether a VLS implementation
>       of the loop could be completely unrolled and become straight-line code.
>       If so, it is generally better to use the VLS version rather
>       than length-agnostic VLA, since the VLA loop would execute an unknown
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index ac93bc07269..e10b5bc0413 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -6,7 +6,7 @@ This file is part of GCC.
>
>  GCC is free software; you can redistribute it and/or modify
>  it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 3, or(at your option)
> +the Free Software Foundation; either version 3, or (at your option)
>  any later version.
>
>  GCC is distributed in the hope that it will be useful,
> @@ -19,21 +19,22 @@ along with GCC; see the file COPYING3.  If not see
>  <http://www.gnu.org/licenses/>.  */
>
>  /* The values of the vl and vtype registers will affect the behavior of RVV
> -   insns. That is, when we need to execute an RVV instruction, we need to set
> +   insns.  That is, when we need to execute an RVV instruction, we need to 
> set
>     the correct vl and vtype values by executing the vsetvl instruction 
> before.
>     Executing the fewest number of vsetvl instructions while keeping the 
> behavior
> -   the same is the problem this pass is trying to solve. This vsetvl pass is
> +   the same is the problem this pass is trying to solve.  This vsetvl pass is
>     divided into 5 phases:
>
>       - Phase 1 (fuse local vsetvl infos): traverses each Basic Block, parses
>         each instruction in it that affects vl and vtype state and generates 
> an
> -       array of vsetvl_info objects. Then traverse the vsetvl_info array from
> -       front to back and perform fusion according to the fusion rules. The 
> fused
> -       vsetvl infos are stored in the vsetvl_block_info object's `infos` 
> field.
> +       array of vsetvl_info objects.  Then traverse the vsetvl_info array 
> from
> +       front to back and perform fusion according to the fusion rules.  The
> +       fused vsetvl infos are stored in the vsetvl_block_info object's 
> `infos`
> +       field.
>
>       - Phase 2 (earliest fuse global vsetvl infos): The header_info and
>         footer_info of vsetvl_block_info are used as expressions, and the
> -       earliest of each expression is computed. Based on the earliest
> +       earliest of each expression is computed.  Based on the earliest
>         information, try to lift up the corresponding vsetvl info to the src
>         basic block of the edge (mainly to reduce the total number of vsetvl
>         instructions, this uplift will cause some execution paths to execute
> @@ -51,9 +52,9 @@ along with GCC; see the file COPYING3.  If not see
>       - Phase 5 (cleanup): Clean up the avl operand in the RVV operator
>         instruction and cleanup the unused dest operand of the vsetvl insn.
>
> -     After the Phase 1 a virtual CFG of vsetvl_info is generated. The virtual
> +     After the Phase 1 a virtual CFG of vsetvl_info is generated.  The 
> virtual
>       basic block is represented by vsetvl_block_info, and the virtual vsetvl
> -     statements inside are represented by vsetvl_info. The later phases 2 
> and 3
> +     statements inside are represented by vsetvl_info.  The later phases 2 
> and 3
>       are constantly modifying and adjusting this virtual CFG. Phase 4 
> performs
>       insertion, modification and deletion of vsetvl instructions based on the
>       optimized virtual CFG. The Phase 1, 2 and 3 do not involve 
> modifications to
> @@ -93,10 +94,10 @@ using namespace riscv_vector;
>
>  /* Set the bitmap DST to the union of SRC of predecessors of
>     basic block B.
> -   It's a bit different from bitmap_union_of_preds in cfganal.cc. This 
> function
> -   takes into account the case where pred is ENTRY basic block. The main 
> reason
> +   It's a bit different from bitmap_union_of_preds in cfganal.cc.  This 
> function
> +   takes into account the case where pred is ENTRY basic block.  The main 
> reason
>     for this difference is to make it easier to insert some special value into
> -   the ENTRY base block. For example, vsetvl_info with a status of UNKNOWN.  
> */
> +   the ENTRY base block.  For example, vsetvl_info with a status of UNKNOWN. 
>  */
>  static void
>  bitmap_union_of_preds_with_entry (sbitmap dst, sbitmap *src, basic_block b)
>  {
> @@ -256,7 +257,7 @@ policy_to_str (bool agnostic_p)
>    return agnostic_p ? "agnostic" : "undisturbed";
>  }
>
> -/* Return true if it is an RVV instruction depends on VTYPE global
> +/* Return true if it is an RVV instruction that depends on VTYPE global
>     status register.  */
>  bool
>  has_vtype_op (rtx_insn *rinsn)
> @@ -485,8 +486,9 @@ get_avl (rtx_insn *rinsn)
>  static bool
>  get_default_ma ()
>  {
> -  /* For the instruction that doesn't require MA, we still need a default 
> value
> -     to emit vsetvl. We pick up the default value according to prefer 
> policy. */
> +  /* For the instruction that does not require MA, we still need a default
> +     value to emit vsetvl.  We pick up the default value according to
> +     preferred policy.  */
>    return (bool) (get_prefer_mask_policy () & 0x1
>                  || (get_prefer_mask_policy () >> 1 & 0x1));
>  }
> @@ -558,7 +560,7 @@ enum def_type
>    BB_END_SET = 1 << 3,
>    /* ??? TODO: In RTL_SSA framework, we have REAL_SET,
>       PHI_SET, BB_HEAD_SET, BB_END_SET and
> -     CLOBBER_DEF def_info types. Currently,
> +     CLOBBER_DEF def_info types.  Currently,
>       we conservatively do not optimize clobber
>       def since we don't see the case that we
>       need to optimize it.  */
> @@ -617,7 +619,7 @@ get_all_real_uses (insn_info *insn, unsigned regno)
>    return uses;
>  }
>
> -/* Recursively find all define instructions. The kind of instruction is
> +/* Recursively find all define instructions.  The kind of instruction is
>     specified by the DEF_TYPE.  */
>  static hash_set<set_info *>
>  get_all_sets (phi_info *phi, unsigned int types)
> @@ -795,7 +797,7 @@ get_all_predecessors (basic_block bb)
>  }
>
>  /* This flags indicates the minimum demand of the vl and vtype values by the
> -   RVV instruction. For example, DEMAND_RATIO_P indicates that this RVV
> +   RVV instruction.  For example, DEMAND_RATIO_P indicates that this RVV
>     instruction only needs the SEW/LMUL ratio to remain the same, and does not
>     require SEW and LMUL to be fixed.
>     Therefore, if the former RVV instruction needs DEMAND_RATIO_P and the 
> latter
> @@ -819,12 +821,12 @@ enum demand_flags : unsigned
>    DEMAND_NON_ZERO_AVL_P = 1 << 7,
>  };
>
> -/* We split the demand information into three parts. They are sew and lmul
> +/* We split the demand information into three parts.  They are sew and lmul
>     related (sew_lmul_demand_type), tail and mask policy related
>     (policy_demand_type) and avl related (avl_demand_type). Then we define 
> three
>     interfaces available_p, compatible_p and merge. available_p is
>     used to determine whether the two vsetvl infos prev_info and next_info are
> -   available or not. If prev_info is available for next_info, it means that 
> the
> +   available or not.  If prev_info is available for next_info, it means that 
> the
>     RVV insn corresponding to next_info on the path from prev_info to 
> next_info
>     can be used without inserting a separate vsetvl instruction. compatible_p
>     is used to determine whether prev_info is compatible with next_info, and 
> if
> @@ -1122,7 +1124,8 @@ public:
>      if (insn->is_debug_insn ())
>        return;
>
> -    /* We set it as unknown since we don't what will happen in CALL or ASM.  
> */
> +    /* We set it as unknown since we don't know what will happen in CALL
> +       or ASM.  */
>      if (insn->is_call () || insn->is_asm ())
>        {
>         set_unknown ();
> @@ -1162,7 +1165,7 @@ public:
>      m_vlmul = ::get_vlmul (insn->rtl ());
>      m_ratio = get_attr_ratio (insn->rtl ());
>      /* when get_attr_ratio is invalid, this kind of instructions
> -       doesn't care about ratio. However, we still need this value
> +       doesn't care about ratio.  However, we still need this value
>         in demand info backward analysis.  */
>      if (m_ratio == INVALID_ATTRIBUTE)
>        m_ratio = calculate_ratio (m_sew, m_vlmul);
> @@ -1303,8 +1306,8 @@ public:
>       if we fuse the VL modification from OTHER into THIS.  */
>    bool vl_modify_non_avl_op_p (const vsetvl_info &other) const
>    {
> -    /* We don't need to worry about any operands from THIS be
> -       modified by OTHER vsetvl since we OTHER vsetvl doesn't
> +    /* We don't need to worry about any operands from THIS being
> +       modified by OTHER vsetvl since OTHER vsetvl doesn't
>         modify any operand.  */
>      if (!other.has_vl ())
>        return false;
> @@ -2467,8 +2470,8 @@ private:
>           continue;
>         else
>           /* We pick the highest probability among those incompatible VSETVL
> -            infos. When all incompatible VSETVL infos have same probability, 
> we
> -            don't pick any of them.  */
> +            infos.  When all incompatible VSETVL infos have same probability,
> +            we don't pick any of them.  */
>           return false;
>        }
>      return true;
> @@ -2835,7 +2838,7 @@ pre_vsetvl::compute_lcm_local_properties ()
>    bitmap_vector_ones (m_transp, last_basic_block_for_fn (cfun));
>
>    /* -  If T is locally available at the end of a block, then T' must be
> -       available at the end of the same block. Since some optimization has
> +       available at the end of the same block.  Since some optimization has
>         occurred earlier, T' might not be locally available, however, it must
>         have been previously computed on all paths. As a formula, T at 
> AVLOC(B)
>         implies that T' at AVOUT(B).
> @@ -3880,7 +3883,7 @@ pass_vsetvl::execute (function *)
>      return 0;
>
>    /* The RVV instruction may change after split which is not a stable
> -     instruction. We need to split it here to avoid potential issue
> +     instruction.  We need to split it here to avoid potential issue
>       since the VSETVL PASS is insert before split PASS.  */
>    split_all_insns ();
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.def 
> b/gcc/config/riscv/riscv-vsetvl.def
> index 2cef36bc4e9..c057ebd20a8 100644
> --- a/gcc/config/riscv/riscv-vsetvl.def
> +++ b/gcc/config/riscv/riscv-vsetvl.def
> @@ -6,7 +6,7 @@ This file is part of GCC.
>
>  GCC is free software; you can redistribute it and/or modify
>  it under the terms of the GNU General Public License as published by
> -the Free Software Foundation; either version 3, or(at your option)
> +the Free Software Foundation; either version 3, or (at your option)
>  any later version.
>
>  GCC is distributed in the hope that it will be useful,
> @@ -22,11 +22,11 @@ along with GCC; see the file COPYING3.  If not see
>     available_p, fuse)
>         prev_demand: the prev vector insn's sew_lmul_type
>         next_demand: the next vector insn's sew_lmul_type
> -       fused_demand: if them are compatible, change prev_info demand to the
> +       fused_demand: if they are compatible, change prev_info demand to the
>                      fused_demand after fuse prev_info and next_info
>         compatible_p: check if prev_demand and next_demand are compatible
>         available_p: check if prev_demand is available for next_demand
> -       fuse: if them are compatible, how to modify prev_info  */
> +       fuse: if they are compatible, how to modify prev_info.  */
>
>  #ifndef DEF_SEW_LMUL_RULE
>  #define DEF_SEW_LMUL_RULE(prev_demand, next_demand, fused_demand,            
>   \
> diff --git a/gcc/config/riscv/riscv-zicfilp.cc 
> b/gcc/config/riscv/riscv-zicfilp.cc
> index de8a6f84216..04d9bd92339 100644
> --- a/gcc/config/riscv/riscv-zicfilp.cc
> +++ b/gcc/config/riscv/riscv-zicfilp.cc
> @@ -44,16 +44,16 @@
>  #include "cgraph.h"
>  #include "output.h"
>
> -/* This pass implements forward-CFI landing pad checks for RISCV. This is
> +/* This pass implements forward-CFI landing pad checks for RISCV.  This is
>     a security feature similar to BTI (branch target identification) in
> -   AArch64 and IBT (indirect branch tracking)in X86. A LPAD (landing-pad
> +   AArch64 and IBT (indirect branch tracking) in X86.  A LPAD (landing-pad
>     check) instruction is used to guard against the execution of
>     instructions which are not the intended target of an indirect branch.
>
>     When forward-CFI is disabled or unimplemented in the CPU, the
> -   landing-pad check label instructions behave as NOP. When implemented in
> +   landing-pad check label instructions behave as NOP.  When implemented in
>     the CPU, and enabled, the destination of an indirect branch must be
> -   LPAD insn. Otherwise, the CPU raises an exception.
> +   LPAD insn.  Otherwise, the CPU raises an exception.
>
>     In order to enable this mechanism, this pass iterates through the
>     control flow of the code and adds appropriate LPAD instructions at the
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 18d6d52b5f3..13c8378c4de 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -109,7 +109,7 @@ along with GCC; see the file COPYING3.  If not see
>  /* Extract the backup dynamic frm rtl.  */
>  #define DYNAMIC_FRM_RTL(c) ((c)->machine->mode_sw_info.dynamic_frm)
>
> -/* True the mode switching has static frm, or false.  */
> +/* True if the mode switching has static frm, or false.  */
>  #define STATIC_FRM_P(c) ((c)->machine->mode_sw_info.static_frm_p)
>
>  #define CFUN_IN_CALL(c) ((c)->machine->mode_sw_info.cfun_call)
> @@ -141,11 +141,11 @@ struct GTY(())  riscv_frame_info {
>    /* How much the GPR save/restore routines adjust sp (or 0 if unused).  */
>    unsigned save_libcall_adjustment;
>
> -  /* the minimum number of bytes, in multiples of 16-byte address increments,
> +  /* The minimum number of bytes, in multiples of 16-byte address increments,
>       required to cover the registers in a multi push & pop.  */
>    unsigned multi_push_adj_base;
>
> -  /* the number of additional 16-byte address increments allocated for the 
> stack
> +  /* The number of additional 16-byte address increments allocated for the 
> stack
>       frame in a multi push & pop.  */
>    unsigned multi_push_adj_addi;
>
> @@ -916,7 +916,7 @@ static const attribute_spec riscv_gnu_attributes[] =
>    {"RVV sizeless type", 4, 4, false, true, false, true, NULL, NULL},
>    {"RVV type", 0, 0, false, true, false, true, NULL, NULL},
>    /* This attribute is used to declare a function, forcing it to use the
> -    standard vector calling convention variant. Syntax:
> +    standard vector calling convention variant.  Syntax:
>      __attribute__((riscv_vector_cc)). */
>    {"riscv_vector_cc", 0, 0, false, true, true, true, NULL, NULL},
>    {"riscv_vls_cc", 0, 1, false, true, true, true,
> @@ -926,13 +926,13 @@ static const attribute_spec riscv_gnu_attributes[] =
>
>       typedef vint8m1_t f_vint8m1_t 
> __attribute__((riscv_rvv_vector_bits(256)));
>
> -     The new created type f_vint8m1_t will be exactly 256 bits.  It can be
> +     The new created type f_vint8m1_t will be exactly 256 bits.  It can
>       be used in globals, structs, unions, and arrays instead of sizeless
>       types.  */
>    {"riscv_rvv_vector_bits", 1, 1, false, true, false, true,
>     riscv_handle_rvv_vector_bits_attribute, NULL},
>    /* This attribute is used to declare a function, forcing it to use the
> -    standard vector calling convention variant. Syntax:
> +    standard vector calling convention variant.  Syntax:
>      __attribute__((norelax)). */
>    {"norelax", 0, 0, true, false, false, false, NULL, NULL},
>  };
> @@ -945,7 +945,7 @@ static const scoped_attribute_specs 
> riscv_gnu_attribute_table  =
>  static const attribute_spec riscv_attributes[] =
>  {
>    /* This attribute is used to declare a function, forcing it to use the
> -     standard vector calling convention variant. Syntax:
> +     standard vector calling convention variant.  Syntax:
>       [[riscv::vector_cc]]. */
>    {"vector_cc", 0, 0, false, true, true, true, NULL, NULL},
>    {"vls_cc", 0, 1, false, true, true, true, 
> riscv_handle_rvv_vls_cc_attribute,
> @@ -955,7 +955,7 @@ static const attribute_spec riscv_attributes[] =
>
>       typedef vint8m1_t f_vint8m1_t 
> __attribute__((riscv_rvv_vector_bits(256)));
>
> -     The new created type f_vint8m1_t will be exactly 256 bits.  It can be
> +     The new created type f_vint8m1_t will be exactly 256 bits.  It can
>       be used in globals, structs, unions, and arrays instead of sizeless
>       types.  */
>    {"rvv_vector_bits", 1, 1, false, true, false, true,
> @@ -1122,7 +1122,7 @@ get_tune_str (const T *opts)
>  }
>
>  /* Return the riscv_tune_info entry for the given name string, return nullptr
> -   if NULL_P is true, otherwise return an placeholder and report error.  */
> +   if NULL_P is true, otherwise return a placeholder and report error.  */
>
>  const struct riscv_tune_info *
>  riscv_parse_tune (const char *tune_string, bool null_p)
> @@ -1457,7 +1457,7 @@ riscv_build_integer_1 (struct riscv_integer_op 
> codes[RISCV_MAX_INTEGER_OPS],
>  /* Fill CODES with a sequence of rtl operations to load VALUE.
>     Return the number of operations needed.
>
> -   ALLOW_NEW_PSEUDOS indicates if or caller wants to allow new pseudo
> +   ALLOW_NEW_PSEUDOS indicates if the caller wants to allow new pseudo
>     registers or not.  This is needed for cases where the integer synthesis 
> and
>     costing code are used in insn conditions, we can't have costing allow
>     recognition at some points and reject at others.  */
> @@ -1989,7 +1989,7 @@ static int riscv_symbol_insns (enum riscv_symbol_type 
> type)
>  }
>
>  /* Immediate values loaded by the FLI.S instruction in Chapter 25 of the 
> latest RISC-V ISA
> -   Manual draft. For details, please see:
> +   Manual draft.  For details, please see:
>     https://github.com/riscv/riscv-isa-manual/releases/tag/isa-449cd0c  */
>
>  static const unsigned HOST_WIDE_INT fli_value_hf[32] =
> @@ -2049,8 +2049,9 @@ const char *fli_value_print[32] =
>    "8.0", "16.0", "128.0", "256.0", "32768.0", "65536.0", "inf", "nan"
>  };
>
> -/* Return index of the FLI instruction table if rtx X is an immediate 
> constant that can
> -   be moved using a single FLI instruction in zfa extension. Return -1 if 
> not found.  */
> +/* Return index of the FLI instruction table if rtx X is an immediate 
> constant
> +   that can be moved using a single FLI instruction in zfa extension.  
> Return -1
> +   if not found.  */
>
>  int
>  riscv_float_const_rtx_index_for_fli (rtx x)
> @@ -2448,7 +2449,7 @@ riscv_v_vls_to_gpr_mode (unsigned vls_mode_size)
>      }
>  }
>
> -/* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct
> +/* Call from ADJUST_NUNITS in riscv-modes.def.  Return the correct
>     NUNITS size for corresponding machine_mode.  */
>
>  poly_int64
> @@ -2464,7 +2465,7 @@ riscv_v_adjust_nunits (machine_mode mode, int scale)
>    return scale;
>  }
>
> -/* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct
> +/* Call from ADJUST_NUNITS in riscv-modes.def.  Return the correct
>     NUNITS size for corresponding machine_mode.  */
>
>  poly_int64
> @@ -2692,7 +2693,7 @@ riscv_address_insns (rtx x, machine_mode mode, bool 
> might_split_p)
>     Return 0 if X isn't a valid constant.
>
>     ALLOW_NEW_PSEUDOS controls whether or not we're going to be allowed
> -   to create new pseduos.  It must be FALSE for any call directly or
> +   to create new pseudos.  It must be FALSE for any call directly or
>     indirectly from a pattern's condition.  */
>
>  int
> @@ -2849,7 +2850,7 @@ riscv_const_insns (rtx x, bool allow_new_pseudos)
>
>      /* TODO: In RVV, we get CONST_POLY_INT by using csrr VLENB
>         instruction and several scalar shift or mult instructions,
> -       it is so far unknown. We set it to 4 temporarily.  */
> +       it is so far unknown.  We set it to 4 temporarily.  */
>      case CONST_POLY_INT:
>        return 4;
>
> @@ -3293,7 +3294,7 @@ riscv_shorten_lw_offset (rtx base, HOST_WIDE_INT offset)
>    return addr;
>  }
>
> -/* Helper for riscv_legitimize_address. Given X, return true if it
> +/* Helper for riscv_legitimize_address.  Given X, return true if it
>     is a left shift by 1, 2 or 3 positions or a multiply by 2, 4 or 8.
>
>     This respectively represent canonical shift-add rtxs or scaled
> @@ -3558,7 +3559,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx 
> dest, rtx src)
>  }
>
>  /* Report when we try to do something that requires vector when vector is
> -   disabled. This is an error of last resort and isn't very high-quality.  It
> +   disabled.  This is an error of last resort and isn't very high-quality.  
> It
>     usually involves attempts to measure the vector length in some way.  */
>
>  static void
> @@ -4376,7 +4377,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
> outer_code, int opno ATTRIBUTE_UN
>      case LABEL_REF:
>      case CONST_DOUBLE:
>        /* With TARGET_SUPPORTS_WIDE_INT const int can't be in CONST_DOUBLE
> -        rtl object. Weird recheck due to switch-case fall through above.  */
> +        rtl object.  Weird recheck due to switch-case fall through above.  */
>        if (GET_CODE (x) == CONST_DOUBLE)
>         gcc_assert (GET_MODE (x) != VOIDmode);
>        /* Fall through.  */
> @@ -5579,7 +5580,7 @@ riscv_extend_comparands (rtx_code code, rtx *op0, rtx 
> *op1)
>    if (GET_MODE_SIZE (word_mode) > GET_MODE_SIZE (GET_MODE 
> (*op0)).to_constant ())
>      {
>        /* It is more profitable to zero-extend QImode values.  But not if the
> -        first operand has already been sign-extended, and the second one is
> +        first operand has already been sign-extended, and the second one
>          is a constant or has already been sign-extended also.  */
>        if (unsigned_condition (code) == code
>           && (GET_MODE (*op0) == QImode
> @@ -6550,8 +6551,8 @@ riscv_pass_aggregate_in_fpr_pair_p (const_tree type,
>         float f;
>       };
>
> -     This case we will got 1, but legacy ABI will got -1, however legacy ABI
> -     will got 1 in later logic, so we should consider this case as 
> compatible.
> +     This case we will get 1, but legacy ABI will get -1, however legacy ABI
> +     will get 1 in later logic, so we should consider this case as 
> compatible.
>    */
>    bool compatible_p = n_new2 == 1 && n_new == -1 && num_fpr == 1;
>
> @@ -6811,8 +6812,8 @@ riscv_get_vector_arg (struct riscv_arg_info *info, 
> const CUMULATIVE_ARGS *cum,
>      }
>
>    /* The number and alignment of vector registers need for this scalable 
> vector
> -     argument. When the mode size is less than a full vector, we use 1 vector
> -     register to pass. Just call TARGET_HARD_REGNO_NREGS for the number
> +     argument.  When the mode size is less than a full vector, we use 1 
> vector
> +     register to pass.  Just call TARGET_HARD_REGNO_NREGS for the number
>       information.  */
>    int nregs = riscv_hard_regno_nregs (V_ARG_FIRST, mode);
>    int LMUL = riscv_tuple_mode_p (mode)
> @@ -7080,7 +7081,7 @@ riscv_pass_aggregate_in_vr (struct riscv_arg_info *info,
>  }
>
>  /* Fill INFO with information about a single argument, and return an RTL
> -   pattern to pass or return the argument. Return NULL_RTX if argument cannot
> +   pattern to pass or return the argument.  Return NULL_RTX if argument 
> cannot
>     pass or return in registers, then the argument may be passed by reference
>     or through the stack.  CUM is the cumulative state for earlier arguments.
>     MODE is the mode of this argument and TYPE is its type (if known).
> @@ -10072,7 +10073,7 @@ riscv_expand_prologue (void)
>    if (need_shadow_stack_push_pop_p ())
>      emit_insn (gen_sspush (Pmode, gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
>
> -  /* prefer multi-push to save-restore libcall.  */
> +  /* Prefer multi-push to save-restore libcall.  */
>    if (riscv_use_multi_push (frame))
>      {
>        remaining_size -= frame->multi_push_adj_base;
> @@ -11329,7 +11330,7 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn 
> *insn, int more)
>  }
>
>  /* Implement TARGET_SCHED_REORDER.  The goal here is to look at the ready
> -   queue and reorder it ever so slightly to encourage issing an insn with
> +   queue and reorder it ever so slightly to encourage issuing an insn with
>     the same vector configuration as the most recently issued vector
>     instruction.  That will reduce vsetvl instructions.  */
>  static int
> @@ -11464,7 +11465,7 @@ riscv_sched_adjust_cost (rtx_insn *, int, rtx_insn 
> *insn, int cost,
>    return new_cost;
>  }
>
> -/* Implement TARGET_SCHED_CAN_SPECULATE_INSN hook.  Return true if insn can
> +/* Implement TARGET_SCHED_CAN_SPECULATE_INSN hook.  Return true if insn
>     can be scheduled for speculative execution.  Reject vsetvl instructions to
>     prevent the scheduler from hoisting them out of basic blocks without
>     checking for data dependencies PR117974.  */
> @@ -11763,7 +11764,7 @@ riscv_convert_vector_chunks (struct gcc_options *opts)
>    if (min_vlen > 32)
>      {
>        /* When targeting minimum VLEN > 32, we should use 64-bit chunk size.
> -        Otherwise we can not include SEW = 64bits.
> +        Otherwise we can not include SEW = 64 bits.
>          Runtime invariant: The single indeterminate represent the
>          number of 64-bit chunks in a vector beyond minimum length of 64 bits.
>          Thus the number of bytes in a vector is 8 + 8 * x1 which is
> @@ -11783,7 +11784,7 @@ riscv_convert_vector_chunks (struct gcc_options *opts)
>    else
>      {
>        /* When targeting minimum VLEN = 32, we should use 32-bit
> -        chunk size. Runtime invariant: The single indeterminate represent the
> +        chunk size.  Runtime invariant: The single indeterminate represent 
> the
>          number of 32-bit chunks in a vector beyond minimum length of 32 bits.
>          Thus the number of bytes in a vector is 4 + 4 * x1 which is
>          riscv_vector_chunks * 4 = poly_int (4, 4).  */
> @@ -11792,10 +11793,10 @@ riscv_convert_vector_chunks (struct gcc_options 
> *opts)
>      }
>
>    /* Set riscv_vector_chunks as poly (1, 1) run-time constant if 
> TARGET_VECTOR
> -     is enabled. Set riscv_vector_chunks as 1 compile-time constant if
> +     is enabled.  Set riscv_vector_chunks as 1 compile-time constant if
>       TARGET_VECTOR is disabled. riscv_vector_chunks is used in 
> "riscv-modes.def"
> -     to set RVV mode size. The RVV machine modes size are run-time constant 
> if
> -     TARGET_VECTOR is enabled. The RVV machine modes size remains default
> +     to set RVV mode size.  The RVV machine modes size are run-time constant 
> if
> +     TARGET_VECTOR is enabled.  The RVV machine modes size remains default
>       compile-time constant if TARGET_VECTOR is disabled.  */
>    if (TARGET_VECTOR_OPTS_P (opts))
>      {
> @@ -12487,7 +12488,7 @@ riscv_function_ok_for_sibcall (tree decl 
> ATTRIBUTE_UNUSED,
>      return false;
>
>    /* Don't use sibcalls in the large model, because a sibcall instruction
> -     expanding and a epilogue expanding both use RISCV_PROLOGUE_TEMP
> +     expanding and an epilogue expanding both use RISCV_PROLOGUE_TEMP
>       register.  */
>    if (riscv_cmodel == CM_LARGE)
>      return false;
> @@ -12814,10 +12815,10 @@ zcmp_additional_adj (HOST_WIDE_INT total, int 
> regs_num)
>  bool
>  riscv_zcmp_valid_stack_adj_bytes_p (HOST_WIDE_INT total, int regs_num)
>  {
> -  HOST_WIDE_INT additioanl_bytes = zcmp_additional_adj (total, regs_num);
> -  return additioanl_bytes == 0 || additioanl_bytes == 1 * ZCMP_SP_INC_STEP
> -        || additioanl_bytes == 2 * ZCMP_SP_INC_STEP
> -        || additioanl_bytes == ZCMP_MAX_SPIMM * ZCMP_SP_INC_STEP;
> +  HOST_WIDE_INT additional_bytes = zcmp_additional_adj (total, regs_num);
> +  return additional_bytes == 0 || additional_bytes == 1 * ZCMP_SP_INC_STEP
> +        || additional_bytes == 2 * ZCMP_SP_INC_STEP
> +        || additional_bytes == ZCMP_MAX_SPIMM * ZCMP_SP_INC_STEP;
>  }
>
>  /* Return true if it's valid gpr_save pattern.  */
> @@ -13106,7 +13107,7 @@ riscv_regmode_natural_size (machine_mode mode)
>         return BYTES_PER_RISCV_VECTOR;
>        else if (!riscv_vls_mode_p (mode))
>         /* For -march=rv64gc_zve32f, the natural vector register size
> -          is 32bits which is smaller than scalar register size, so we
> +          is 32 bits which is smaller than scalar register size, so we
>            return minimum size between vector register size and scalar
>            register size.  */
>         return MIN (size.to_constant (), UNITS_PER_WORD);
> @@ -13603,7 +13604,7 @@ vxrm_unknown_p (rtx_insn *insn)
>    if (reg_set_p (gen_rtx_REG (SImode, VXRM_REGNUM), insn))
>      return true;
>
> -  /* Return true for all assembly since users may hardcode a assembly
> +  /* Return true for all assembly since users may hardcode an assembly
>       like this: asm volatile ("csrwi vxrm, 0").  */
>    if (asm_insn_p (insn))
>      return true;
> @@ -15460,7 +15461,7 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
>
>    /* The number of instructions to synthesize the constant is a good
>       estimate of the budget.  That does not account for out of order
> -     execution an fusion in the constant synthesis those would naturally
> +     execution and fusion in the constant synthesis those would naturally
>       decrease the budget.  It also does not account for the IOR/XOR at
>       the end of the sequence which would increase the budget.  */
>    int budget = (TARGET_ZBS ? riscv_const_insns (operands[2], true) : -1);
> @@ -15479,7 +15480,7 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
>        budget--;
>      }
>
> -  /* Check for bseti cases. For each remaining bit in ival,
> +  /* Check for bseti cases.  For each remaining bit in ival,
>       decrease the budget by one. */
>    while (ival)
>      {
> @@ -15697,7 +15698,7 @@ synthesize_and (rtx operands[3])
>
>    /* The number of instructions to synthesize the constant is a good
>       estimate of the budget.  That does not account for out of order
> -     execution an fusion in the constant synthesis those would naturally
> +     execution and fusion in the constant synthesis those would naturally
>       decrease the budget.  It also does not account for the AND at
>       the end of the sequence which would increase the budget. */
>    int budget = riscv_const_insns (operands[2], true);
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index c2e5551aeaf..b98a4a4df60 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -177,7 +177,8 @@ ARCH_UNSET_CLEANUP_SPECS \
>
>  /* The `Q' extension is not yet supported.  */
>  #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
> -/* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, 
> size = poly (8, 8). */
> +/* Size per vector register.  For VLEN = 32, size = poly (4, 4).
> +   Otherwise, size = poly (8, 8).  */
>  #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk)
>
>  /* The largest type that can be passed in floating-point registers.  */
> @@ -1328,7 +1329,7 @@ extern void riscv_remove_unneeded_save_restore_calls 
> (void);
>                 STACK_BOUNDARY / BITS_PER_UNIT)            \
>      : (crtl->outgoing_args_size + STACK_POINTER_OFFSET))
>
> -/* According to the RISC-V C API, the arch string may contains ','. To avoid
> +/* According to the RISC-V C API, the arch string may contain ','.  To avoid
>     the conflict with the default separator, we choose '#' as the separator 
> for
>     the target attribute.  */
>  #define TARGET_CLONES_ATTR_SEPARATOR '#'
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index f308924c53f..5f9f26ee63f 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -748,7 +748,7 @@ (define_expand "addsi3"
>           || (TARGET_64BIT && synthesize_add_extended (operands))))
>      DONE;
>
> -  /* Constants have already been handled already.  */
> +  /* Constants have already been handled.  */
>    if (TARGET_64BIT)
>      {
>        rtx tdest = gen_reg_rtx (DImode);
> @@ -3148,7 +3148,7 @@ (define_insn "*lshrsi3_zero_extend_3"
>    [(set_attr "type" "shift")
>     (set_attr "mode" "SI")])
>
> -;; Canonical form for a extend of a logical shift right (sign/zero 
> extraction).
> +;; Canonical form for an extend of a logical shift right (sign/zero 
> extraction).
>  ;; Special cases, that are ignored (handled elsewhere):
>  ;; * Single-bit extraction (Zbs/XTheadBs)
>  ;; * Single-bit extraction (Zicondops/XVentanaCondops)
> @@ -3245,7 +3245,7 @@ (define_split
>    unsigned HOST_WIDE_INT mask = INTVAL (operands[3]);
>    int leading  = clz_hwi (mask);
>    int trailing = ctz_hwi (mask);
> -
> +
>    operands[5] = GEN_INT (leading + trailing);
>    operands[6] = GEN_INT (leading);
>  })
> @@ -4786,7 +4786,7 @@ (define_expand "strlen<mode>"
>      FAIL;
>  })
>
> -; Split (A<<1) | (A>=0) into a rotate + xor. Using two’s-complement 
> identities:
> +; Split (A<<1) | (A>=0) into a rotate + xor.  Using two’s-complement 
> identities:
>  ; (A>=0) == ((A >> (W-1)) ^ 1) and (A<<1) | (A>>(W-1)) == ROL1 (A), so the 
> whole
>  ; expression equals ROL1 (A) ^ 1.
>  (define_split
> @@ -4814,7 +4814,7 @@ (define_insn "*large_load_address"
>    [(set_attr "type" "load")
>     (set (attr "length") (const_int 8))])
>
> -;; The AND is redundant here.  It always turns off the high 32 bits  and the
> +;; The AND is redundant here.  It always turns off the high 32 bits and the
>  ;; low number of bits equal to the shift count.  Those upper 32 bits will be
>  ;; reset by the SIGN_EXTEND at the end.
>  ;;
> diff --git a/gcc/config/riscv/sifive-vector-builtins-functions.def 
> b/gcc/config/riscv/sifive-vector-builtins-functions.def
> index ecfcd0e03b3..fcd520c057e 100644
> --- a/gcc/config/riscv/sifive-vector-builtins-functions.def
> +++ b/gcc/config/riscv/sifive-vector-builtins-functions.def
> @@ -11,11 +11,11 @@ any later version.
>
>  GCC is distributed in the hope that it will be useful,
>  but WITHOUT ANY WARRANTY; without even the implied warranty of
> -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>  GNU General Public License for more details.
>
>  You should have received a copy of the GNU General Public License
> -along with GCC; see the file COPYING3. If not see
> +along with GCC; see the file COPYING3.  If not see
>  <http://www.gnu.org/licenses/>. */
>
>  /* Use "DEF_RVV_FUNCTION" macro to define RVV intrinsic functions.
> diff --git a/gcc/config/riscv/sifive_vector.h 
> b/gcc/config/riscv/sifive_vector.h
> index 841e7c8a64a..fd975b51931 100644
> --- a/gcc/config/riscv/sifive_vector.h
> +++ b/gcc/config/riscv/sifive_vector.h
> @@ -31,7 +31,7 @@
>  #define __riscv_intrinsic_xsfvqmaccqoq 1
>
>  /* TODO: This should have a separate pragma to include only the SiFive
> -         vector intrinsics. For now, we are including riscv_vector.h. */
> +       vector intrinsics.  For now, we are including riscv_vector.h.  */
>  #include <riscv_vector.h>
>
>  #endif // __SIFIVE_VECTOR_H
> diff --git a/gcc/config/riscv/spacemit-x60.md 
> b/gcc/config/riscv/spacemit-x60.md
> index 1d288fde896..5240655f458 100644
> --- a/gcc/config/riscv/spacemit-x60.md
> +++ b/gcc/config/riscv/spacemit-x60.md
> @@ -24,7 +24,7 @@
>  ;; 2*alu + 2*lsu + 1*fpalu + 1*fdivsqrt + 1*vxu
>  ;;
>  ;; There's actually two VXU units and ops get split across them
> -;; to give the illusion of a single wider unit with higher
> +;; to give the illusion of a single wider unit with higher
>  ;; performance.  There are a few ops that can only be fed into
>  ;; one of the two units.  For the purposes of this scheduling
>  ;; model, the VXU is treated as a single unit.
> diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
> index b143900939d..b16b2c443be 100644
> --- a/gcc/config/riscv/thead.cc
> +++ b/gcc/config/riscv/thead.cc
> @@ -143,7 +143,7 @@ th_mempair_output_move (rtx operands[4], bool load_p,
>  /* Analyze if a pair of loads/stores MEM1 and MEM2 with given MODE
>     are consecutive so they can be merged into a mempair instruction.
>     RESERVED will be set to true, if a reversal of the accesses is
> -   required (false otherwise). Returns true if the accesses can be
> +   required (false otherwise).  Returns true if the accesses can be
>     merged (even if reversing is necessary) and false if not.  */
>
>  static bool
> @@ -291,7 +291,7 @@ th_mempair_operands_p (rtx operands[4], bool load_p,
>    if (!th_mempair_check_consecutive_mems (mode, &mem_1, &mem_2, &reversed))
>      return false;
>
> -  /* If necessary, reverse the local copy of the operands to simplify
> +  /* If necessary, reverse the local copy of the operands to simplify
>       testing of alignments and mempair operand.  */
>    if (reversed)
>      {
> @@ -372,7 +372,7 @@ th_mempair_restore_regs (rtx operands[4])
>  }
>
>  /* Prepare the OPERANDS array to emit a mempair instruction using the
> -   provided information. No checks are performed, the resulting array
> +   provided information.  No checks are performed, the resulting array
>     should be validated using th_mempair_operands_p().  */
>
>  void
> @@ -535,8 +535,8 @@ th_memidx_legitimate_modify_p (rtx x, bool post)
>  }
>
>  /* Provide a buffer for a th.lXia/th.lXib/th.sXia/th.sXib instruction
> -   for the given MODE. If LOAD is true, a load instruction will be
> -   provided (otherwise, a store instruction). If X is not suitable
> +   for the given MODE.  If LOAD is true, a load instruction will be
> +   provided (otherwise, a store instruction).  If X is not suitable
>     return NULL.  */
>
>  static const char *
> @@ -789,8 +789,8 @@ th_memidx_legitimate_index_p (rtx x, bool uindex)
>  }
>
>  /* Provide a buffer for a th.lrX/th.lurX/th.srX/th.surX instruction
> -   for the given MODE. If LOAD is true, a load instruction will be
> -   provided (otherwise, a store instruction). If X is not suitable
> +   for the given MODE.  If LOAD is true, a load instruction will be
> +   provided (otherwise, a store instruction).  If X is not suitable
>     return NULL.  */
>
>  static const char *
> @@ -831,8 +831,8 @@ th_memidx_output_index (rtx dest, rtx src, machine_mode 
> mode, bool load)
>  }
>
>  /* Provide a buffer for a th.flX/th.fluX/th.fsX/th.fsuX instruction
> -   for the given MODE. If LOAD is true, a load instruction will be
> -   provided (otherwise, a store instruction). If X is not suitable
> +   for the given MODE.  If LOAD is true, a load instruction will be
> +   provided (otherwise, a store instruction).  If X is not suitable
>     return NULL.  */
>
>  static const char *
> @@ -899,7 +899,7 @@ th_classify_address (struct riscv_address_info *info, rtx 
> x,
>  /* Provide a string containing a XTheadMemIdx instruction for the given
>     MODE from the provided SRC to the provided DEST.
>     A pointer to a NULL-terminated string containing the instruction will
> -   be returned if a suitable instruction is available. Otherwise, this
> +   be returned if a suitable instruction is available.  Otherwise, this
>     function returns NULL.  */
>
>  const char *
> diff --git a/gcc/config/riscv/tt-ascalon-d8.md 
> b/gcc/config/riscv/tt-ascalon-d8.md
> index bd9efe5e824..7f7ed18004c 100644
> --- a/gcc/config/riscv/tt-ascalon-d8.md
> +++ b/gcc/config/riscv/tt-ascalon-d8.md
> @@ -94,7 +94,7 @@ (define_insn_reservation "tt_ascalon_d8_imul" 3
>
>  ;; Integer division is not pipelined.  Do not block the unit for more than
>  ;; three cycles so the DFA does not get too large.  Similar for other
> -;; non-pipelined instructions. Division is variable cycles so pick a value
> +;; non-pipelined instructions.  Division is variable cycles so pick a value
>  ;; in the middle.
>  (define_insn_reservation "tt_ascalon_d8_idiv" 15
>    (and (eq_attr "tune" "tt_ascalon_d8")
> diff --git a/gcc/config/riscv/vector-crypto.md 
> b/gcc/config/riscv/vector-crypto.md
> index f62d016bb03..b12a8453eb1 100644
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -141,7 +141,7 @@ (define_insn "@pred_vandn<mode>_scalar"
>    [(set_attr "type" "vandn")
>     (set_attr "mode" "<MODE>")])
>
> -;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
> +;; Handle GET_MODE_INNER (mode) = DImode.  We need to split them since
>  ;; we need to deal with SEW = 64 in RV32 system.
>  (define_expand "@pred_vandn<mode>_scalar"
>    [(set (match_operand:V_VLSI_D 0 "register_operand")
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index 902f1648675..62a1eb3fbc0 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -4742,7 +4742,7 @@ (define_mode_attr vnnconvert [
>  ;; Due to we cannot define a mode_attr mapping one HF to both
>  ;; the SI and DI, we use 2 different mode_atter to cover all
>  ;; the combination as above, as well as the different iterator
> -;; for the lrint<m><n> patterns. Aka:
> +;; for the lrint<m><n> patterns.  Aka:
>  ;;
>  ;; V_F2SI_CONVERT: (HF, SF, DF) => SI
>  ;; V_F2DI_CONVERT: (HF, SF, DF) => DI
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 136ecdc787e..dfd333f525e 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -85,10 +85,10 @@ (define_attr "has_vl_op" "false,true"
>          (const_string "true")]
>         (const_string "false")))
>
> -;; The default SEW of RVV instruction. This attribute doesn't mean the 
> instruction
> -;; is necessary to require SEW check for example vlm.v which require ratio to
> -;; check. However, we need default value of SEW for vsetvl instruction since 
> there
> -;; is no field for ratio in the vsetvl instruction encoding.
> +;; The default SEW of RVV instruction.  This attribute doesn't mean the
> +;; instruction is necessary to require SEW check for example vlm.v which 
> require
> +;; ratio to check.  However, we need default value of SEW for vsetvl 
> instruction
> +;; since there is no field for ratio in the vsetvl instruction encoding.
>  (define_attr "sew" ""
>    (cond [(eq_attr "mode" "RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\
>                           
> RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,\
> @@ -1001,7 +1001,7 @@ (define_attr "avl_type_idx" ""
>            (const_int 4)]
>         (const_int INVALID_ATTRIBUTE)))
>
> -;; Defines rounding mode of an fixed-point operation.
> +;; Defines rounding mode of a fixed-point operation.
>
>  (define_attr "vxrm_mode" "rnu,rne,rdn,rod,clobber,none"
>    (cond [(eq_attr "type" "vaalu,vsmul,vsshift,vnclip")
> @@ -1022,7 +1022,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,clobber,none"
>          (const_string "clobber")]
>          (const_string "none")))
>
> -;; Defines rounding mode of an floating-point operation.
> +;; Defines rounding mode of a floating-point operation.
>  (define_attr "frm_mode" ""
>    (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
>          (symbol_ref "riscv_vector::FRM_DYN")]
> @@ -1188,7 +1188,7 @@ (define_expand "mov<mode>"
>          registers.
>
>         - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
> -        before spilling. The clobber scratch is used by spilling fractional
> +        before spilling.  The clobber scratch is used by spilling fractional
>          registers in IRA/LRA so it's too early.  */
>    if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], <MODE>mode))
>      {
> @@ -1223,7 +1223,9 @@ (define_expand "mov<mode>"
>  ;;       (clobber (reg:SI 14 a4 [149]))])
>  ;; So that we could be able to emit vsetvl instruction using clobber scratch 
> a4.
>  ;; To let LRA generate the expected pattern, we should exclude fractional 
> vector
> -;; load/store in "*mov<mode>_whole". Otherwise, it will reload this pattern 
> into:
> +;; load/store in "*mov<mode>_whole".  Otherwise, it will reload this pattern
> +;; into:
> +
>  ;;  (insn 20 19 9 2 (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
>  ;;           (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] 
> A8])))
>  ;; which is not the pattern we want.
> @@ -1686,10 +1688,10 @@ (define_insn_and_split "*vec_duplicate<mode>"
>  ;; VL/VTYPE global registers status after "insert-vsetvl" PASS.
>
>  ;; -  "@vsetvl<mode>_no_side_effects" has no side effects and excludes 
> VL/VTYPE
> -;; global registers status (define set). It's only used by GCC standard 
> pattern
> -;; expansion. For example: "mov<mode>" pattern for fractional vector modes 
> which
> -;; need to set VL/VTYPE. Then we could manually call this pattern to gain 
> benefits
> -;; from the optimization of each GCC internal PASS.
> +;; global registers status (define set).  It's only used by GCC standard 
> pattern
> +;; expansion.  For example: "mov<mode>" pattern for fractional vector modes
> +;; which need to set VL/VTYPE.  Then we could manually call this pattern to 
> gain
> +;; benefits from the optimization of each GCC internal PASS.
>
>  ;; 1. void foo (float *in, float *out)
>  ;;    {
> @@ -1860,9 +1862,9 @@ (define_insn_and_split "@vsetvl<mode>_no_side_effects"
>  ;; The reason we can remove signe_extend is because currently the vl value
>  ;; returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and
>  ;; bits 17 to 63 (including 31) are always 0, so there is no change after
> -;; sign_extend. Note that for HI and QI modes we cannot do this.
> +;; sign_extend.  Note that for HI and QI modes we cannot do this.
>  ;; Of course, if the range of instructions returned by vsetvl later expands
> -;; to 32bits, then this combine pattern needs to be removed. But that could 
> be
> +;; to 32 bits, then this combine pattern needs to be removed.  But that 
> could be
>  ;; a long time from now.
>  (define_insn_and_split "*vsetvldi_no_side_effects_si_extend"
>    [(set (match_operand:DI 0 "register_operand")
> @@ -2949,7 +2951,7 @@ (define_insn "@pred_sub<mode>_reverse_scalar"
>    [(set_attr "type" "vialu")
>     (set_attr "mode" "<MODE>")])
>
> -;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
> +;; Handle GET_MODE_INNER (mode) = DImode.  We need to split them since
>  ;; we need to deal with SEW = 64 in RV32 system.
>  (define_expand "@pred_<optab><mode>_scalar"
>    [(set (match_operand:V_VLSI_D 0 "register_operand")
> @@ -4732,7 +4734,7 @@ (define_insn "@pred_<sat_op><mode>_scalar"
>    [(set_attr "type" "<sat_insn_type>")
>     (set_attr "mode" "<MODE>")])
>
> -;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
> +;; Handle GET_MODE_INNER (mode) = DImode.  We need to split them since
>  ;; we need to deal with SEW = 64 in RV32 system.
>  (define_expand "@pred_<sat_op><mode>_scalar"
>    [(set (match_operand:V_VLSI_D 0 "register_operand")
> @@ -5117,7 +5119,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
>     (set_attr "mode" "<MODE>")
>     (set_attr "spec_restriction" "none,thv,thv,none,none")])
>
> -;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
> +;; Handle GET_MODE_INNER (mode) = DImode.  We need to split them since
>  ;; we need to deal with SEW = 64 in RV32 system.
>  (define_expand "@pred_cmp<mode>_scalar"
>    [(set (match_operand:<VM> 0 "register_operand")
> @@ -6178,8 +6180,8 @@ (define_insn "@pred_widen_mul_plusus<mode>_scalar"
>  ;; 
> -------------------------------------------------------------------------------
>
>  ;; We keep this pattern same as pred_mov so that we can gain more 
> optimizations.
> -;; For example, if we have vmxor.mm v1,v1,v1. It will be optimized as 
> vmclr.m which
> -;; is generated by pred_mov.
> +;; For example, if we have vmxor.mm v1,v1,v1.  It will be optimized
> +;; as vmclr.m which is generated by pred_mov.
>  (define_insn "@pred_<optab><mode>"
>    [(set (match_operand:VB_VLS 0 "register_operand"                   "=vr")
>         (if_then_else:VB_VLS
> diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
> index 34fe2ce29c6..522b0e75cd8 100644
> --- a/gcc/config/riscv/zicond.md
> +++ b/gcc/config/riscv/zicond.md
> @@ -126,7 +126,7 @@ (define_split
>  })
>
>  ;; In some cases gimple can give us a sequence with a logical and
> -;; of two sCC insns.  This can be implemented an sCC feeding a
> +;; of two sCC insns.  This can be implemented with an sCC feeding a
>  ;; conditional zero.
>  ;;
>  ;; AND is commutative, so every form has two variants
> @@ -224,7 +224,7 @@ (define_split
>                                       (match_dup 5)))]
>    { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })
>
> -;; We can splat the sign bit across a GPR with a arithmetic right shift
> +;; We can splat the sign bit across a GPR with an arithmetic right shift
>  ;; which gives us a 0, -1 result.  We then turn on bit #0 unconditionally
>  ;; which results in 1, -1.  There's probably other cases that could be
>  ;; handled, this seems particularly important though.
> @@ -245,7 +245,7 @@ (define_split
>  ;; Similarly, but the condition and true/false values are reversed
>  ;;
>  ;; Note the case where the condition is reversed, but not the true/false
> -;; values.  Or vice-versa is not handled because we don't support 4->3
> +;; values.  Or vice versa is not handled because we don't support 4->3
>  ;; splits.
>  (define_split
>    [(set (match_operand:X 0 "register_operand")
> @@ -288,7 +288,7 @@ (define_split
>  ;; in the two arms.
>
>  ;; Simple rv32 or rv64 ops where we can zero either operand to make
> -;; it neutral.  Two as the the common and potentially neutral op in
> +;; it neutral.  Two as the common and potentially neutral op in
>  ;; the 2nd if-then-else can be swapped.
>  (define_split
>    [(set (match_operand:X 0 "register_operand")
> diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi
> index 9ef9dd5946d..0f774c560d6 100644
> --- a/gcc/doc/riscv-mcpu.texi
> +++ b/gcc/doc/riscv-mcpu.texi
> @@ -13,7 +13,7 @@
>  @opindex mcpu
>  @item -mcpu=@var{processor-string}
>  Use architecture of and optimize the output for the given processor, 
> specified
> -by particular CPU name. Permissible values for this option are:
> +by particular CPU name.  Permissible values for this option are:
>
>
>  @samp{sifive-e20},
> --
> 2.52.0
>