I was testing spec2017 late last week on the K3 design and stumbled
across a couple of functional fails.
In this particular case we mis-compiled omnet, thankfully in such a way
that it didn't really run at all, so time to failure was exceedingly short.
A couple months ago I extended our ability to recognize more czero
sequences, particularly in cases where we're combining the output of 2
or more sCC style insns. I took a bit of a short-cut and adjusted the
code on a node I knew would not be shared in the IL when doing a split.
I should have known better. PUT_MODE and PUT_CODE are generally bad to
use and I've called out others for similar changes.
Consider if we're doing a 3->2 split, but when one of the two split
insns do not match. In that scenario the PUT_CODE trick is going to
cause problems because we change the IL, but the transformation as a
whole isn't applied. In this case we're inverting the mode (EQ->NE and
NE->EQ), the net is we flip the tense of a branch/sCC.
I never narrowed down a testcase. This was found by inspecting codegen
and dump differences after bisecting to a change and bisecting down to a
single .o file.
This fixes the omnet failure. There's a second cluster of failures
(502.gcc) which are unrelated and I'm still debugging those failures.
Bootstrapped and regression tested on riscv64. Of course the original
patch survived that test as well, so perhaps take it with a mountain of
salt rather than the usual grain... Waiting on pre-commit before moving
forward.
Jeff
* config/riscv/zicond.md (combined sCC splitters): Avoid using
PUT_MODE to change existing RTL. Instead just generate a new node.
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 34fe2ce29c6d..346ab1b64b32 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -143,7 +143,10 @@ (define_split
[(match_dup 2) (const_int 0)])
(const_int 0)
(match_dup 5)))]
- { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })
+ { operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == EQ ? NE : EQ,
+ GET_MODE (operands[1]),
+ operands[2],
+ CONST0_RTX (GET_MODE (operands[1]))); })
(define_split
[(set (match_operand:X 0 "register_operand")
@@ -158,7 +161,10 @@ (define_split
[(match_dup 2) (const_int 0)])
(const_int 0)
(match_dup 5)))]
- { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })
+ { operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == EQ ? NE : EQ,
+ GET_MODE (operands[1]),
+ operands[2],
+ CONST0_RTX (GET_MODE (operands[1]))); })
;; Similarly but GE/GEU which requires (const_int 1) as an operand.
@@ -175,7 +181,10 @@ (define_split
[(match_dup 2) (const_int 0)])
(const_int 0)
(match_dup 4)))]
- { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })
+ { operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == EQ ? NE : EQ,
+ GET_MODE (operands[1]),
+ operands[2],
+ CONST0_RTX (GET_MODE (operands[1]))); })
(define_split
[(set (match_operand:X 0 "register_operand")
@@ -190,7 +199,10 @@ (define_split
[(match_dup 2) (const_int 0)])
(const_int 0)
(match_dup 4)))]
- { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })
+ { operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == EQ ? NE : EQ,
+ GET_MODE (operands[1]),
+ operands[2],
+ CONST0_RTX (GET_MODE (operands[1]))); })
;; Similarly but LU/LTU which allows an arith_operand
(define_split
@@ -206,7 +218,10 @@ (define_split
[(match_dup 2) (const_int 0)])
(const_int 0)
(match_dup 5)))]
- { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })
+ { operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == EQ ? NE : EQ,
+ GET_MODE (operands[1]),
+ operands[2],
+ CONST0_RTX (GET_MODE (operands[1]))); })
;; Finally LE/LEU which requires sle_operand.
(define_split
@@ -222,7 +237,10 @@ (define_split
[(match_dup 2) (const_int 0)])
(const_int 0)
(match_dup 5)))]
- { PUT_CODE (operands[1], GET_CODE (operands[1]) == EQ ? NE : EQ); })
+ { operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == EQ ? NE : EQ,
+ GET_MODE (operands[1]),
+ operands[2],
+ CONST0_RTX (GET_MODE (operands[1]))); })
;; We can splat the sign bit across a GPR with a arithmetic right shift
;; which gives us a 0, -1 result. We then turn on bit #0 unconditionally
