From: Robert Suchanek <[email protected]>
These reloads happen because of different modes making elimination
non-trivial.
gcc/
* config/mips/mips.md: Add peepholes to remove silly moves.
gcc/testsuite/
* gcc.target/mips/mips16-redundant-moves-1.c: New test.
Cherry-picked 85462a9dbf8d659bfb0417d354a0a4f9cd4b8e07
from https://github.com/MIPS/gcc
Signed-off-by: Robert Suchanek <[email protected]>
Signed-off-by: Faraz Shahbazker <[email protected]>
Signed-off-by: Aleksandar Rakic <[email protected]>
Signed-off-by: Eldar Osmanovic <[email protected]>
---
gcc/config/mips/mips.md | 24 +++++++++++
.../mips/mips16-redundant-moves-1.c | 42 +++++++++++++++++++
2 files changed, 66 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/mips/mips16-redundant-moves-1.c
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index c1507b9b825..032b8260f8b 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -5172,6 +5172,18 @@
[(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
(set_attr "mode" "HI")])
+(define_peephole2
+ [(set (match_operand:HI 0 "register_operand")
+ (match_operand:HI 1 "register_operand"))
+ (set (match_operand:SI 2 "register_operand")
+ (match_operand:SI 3 "register_operand"))]
+ "TARGET_MIPS16
+ && REGNO (operands[1]) == REGNO (operands[2])
+ && REGNO (operands[0]) == REGNO (operands[3])
+ && peep2_reg_dead_p (2, operands[3])"
+ [(const_int 0)]
+ "")
+
;; On the mips16, we can split lh $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
;; load are 2 2 byte instructions.
@@ -5248,6 +5260,18 @@
[(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
(set_attr "mode" "QI")])
+(define_peephole2
+ [(set (match_operand:QI 0 "register_operand")
+ (match_operand:QI 1 "register_operand"))
+ (set (match_operand:SI 2 "register_operand")
+ (match_operand:SI 3 "register_operand"))]
+ "TARGET_MIPS16
+ && REGNO (operands[1]) == REGNO (operands[2])
+ && REGNO (operands[0]) == REGNO (operands[3])
+ && peep2_reg_dead_p (2, operands[3])"
+ [(const_int 0)]
+ "")
+
;; On the mips16, we can split lb $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
;; load are 2 2 byte instructions.
diff --git a/gcc/testsuite/gcc.target/mips/mips16-redundant-moves-1.c
b/gcc/testsuite/gcc.target/mips/mips16-redundant-moves-1.c
new file mode 100644
index 00000000000..5403df0e204
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/mips16-redundant-moves-1.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-mips16 isa_rev<=5 -mgp32 -fdump-rtl-peephole2" } */
+/* { dg-skip-if "requires -O2" { *-*-* } { "*" } { "-O2" } } */
+/* { dg-skip-if "requires non-LTO" { *-*-* } { "-flto" } { "" } } */
+
+int __RTL (startwith ("peephole2")) hi_move ()
+{
+(function "hi_move"
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 4 (set (reg:HI $2)
+ (reg:HI $3)))
+ (cinsn 5 (set (reg:SI $3)
+ (reg:SI $2)))
+ (cinsn 6 (use (reg:SI $3)))
+ (edge-to exit (flags "FALLTHRU"))
+ )
+ )
+)
+}
+
+int __RTL (startwith ("peephole2")) qi_move ()
+{
+(function "qi_move"
+ (insn-chain
+ (block 2
+ (edge-from entry (flags "FALLTHRU"))
+ (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK)
+ (cinsn 4 (set (reg:QI $4)
+ (reg:QI $5)))
+ (cinsn 5 (set (reg:SI $5)
+ (reg:SI $4)))
+ (cinsn 6 (use (reg:SI $5)))
+ (edge-to exit (flags "FALLTHRU"))
+ )
+ )
+)
+}
+
+/* { dg-final { scan-rtl-dump-times "Splitting with gen_peephole2" 2
"peephole2" } } */
--
2.43.0
