On 6/19/26 12:51 PM, Jeffrey Law wrote:
> OK. We could infinitely recurse if there's a loop in the alias
> mappings, but I doubt that's worth tryign to bullet proof against since
> that would be considered a bug in the alias mapping itself.
Yes, but I'm fairly certain that would be caught fairly early in
testing of the patch that adds that loop, so I doubt we'd ever see
that in a patch submitted to the mailing list...unless it was totally
untested.
>> gcc/
>> * config/riscv/riscv-cores.def (RISCV_TUNE)<tt-ascalon-d8>: Rename from
>> this...
>> (RISCV_TUNE)<tt-ascalon-x>: ...to this.
>> (RISCV_CORE)<tt-ascalon-d8>: Likewise.
>> (RISCV_CORE)<tt-ascalon-x>: Likewise.
>> (RISCV_CORE_ALIAS): Add tt-ascalon-d8 alias for tt-ascalon-x.
>> * doc/riscv-mcpu.texi: Document the name change.
>> * doc/riscv-mtune.texi: Likewise.
>
> OK. Of course. Now if we could just stop marketing folks from changing
> names. Of course I've been fighting that for 30+ years and losing.
I can neither confirm nor deny that the same has happened to me. :-)
I would like to backport the tt-ascalon-x name change to the GCC 16 and 15
branches, since Ascalon support exists in both of those releases, but for safety
reasons, maybe we should just go with a core/tune duplication method, rather
than backporting the new core alias support too. Ala the untested patch below.
Thoughts?
Peter
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 79a460f8176..3723b6cf07a 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -40,6 +40,7 @@ RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
+RISCV_TUNE("tt-ascalon-x", tt_ascalon_d8, tt_ascalon_d8_tune_info)
RISCV_TUNE("tt-ascalon-d8", tt_ascalon_d8, tt_ascalon_d8_tune_info)
RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
RISCV_TUNE("xt-c908", generic, generic_ooo_tune_info)
@@ -148,6 +149,10 @@ RISCV_CORE("xt-c920v2",
"rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_"
"xtheadsync",
"xt-c920v2")
+RISCV_CORE("tt-ascalon-x",
"rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_"
+ "zvfh_zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_"
+ "smstateen_ssaia_ssstrict_svadu",
+ "tt-ascalon-x")
RISCV_CORE("tt-ascalon-d8",
"rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_"
"zvfh_zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_"
"smstateen_ssaia_ssstrict_svadu",
diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi
index f7b03a8f40f..46fb9b9fc33 100644
--- a/gcc/doc/riscv-mcpu.texi
+++ b/gcc/doc/riscv-mcpu.texi
@@ -60,7 +60,7 @@ by particular CPU name. Permissible values for this option
are:
@samp{xt-c920v2},
-@samp{tt-ascalon-d8},
+@samp{tt-ascalon-x},
@samp{xiangshan-nanhu},
diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi
index 6865bd6fbf7..d1f67a795f4 100644
--- a/gcc/doc/riscv-mtune.texi
+++ b/gcc/doc/riscv-mtune.texi
@@ -30,7 +30,7 @@ particular CPU name. Permissible values for this option are:
@samp{sifive-p600-series},
-@samp{tt-ascalon-d8},
+@samp{tt-ascalon-x},
@samp{thead-c906},
