On 6/19/26 6:21 PM, Peter Bergner wrote: > On 6/19/26 5:30 PM, Jeffrey Law wrote: >> Either works for me. If we go with the backport, then I'd suggest >> letting it simmer on the trunk for a week or so. While I don't expect >> problems, the soak time never hurts. Duplication is safer, but >> obviously would require more maintenance if we find something needs to >> change in the ascalon bits. >> >> Ultimately, your call. I'll support either approach.
I went with the method of duplicating the entries as I wanted to be super safe and I don't expect to have to make any further changes that would require making the same change in two different places. I have attached the patch I pushed to the gcc-16 release branch below. I still have to check the gcc-15 release branch to see whether it requires any other changes beyond this. I'll report back on that later. Peter riscv: Add -mcpu= and -mtune = support for tt-ascalon-x The Ascalon cpu's official marketing name is Ascalon X. Add support for the -mcpu= and -mtune= options to accept tt-ascalon-x as the cpu's name in addition to the older tt-ascalon-d8 name. 2026-06-25 Peter Bergner <[email protected]> gcc/ * config/riscv/riscv-cores.def (RISCV_TUNE): Add tt-ascalon-x. (RISCV_CORE): Likewise. * doc/riscv-mcpu.texi: Regenerate. * doc/riscv-mtune.texi: Likewise. Signed-off-by: Peter Bergner <[email protected]> --- gcc/config/riscv/riscv-cores.def | 5 +++++ gcc/doc/riscv-mcpu.texi | 2 ++ gcc/doc/riscv-mtune.texi | 2 ++ 3 files changed, 9 insertions(+) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 79a460f8176..3723b6cf07a 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -40,6 +40,7 @@ RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) +RISCV_TUNE("tt-ascalon-x", tt_ascalon_d8, tt_ascalon_d8_tune_info) RISCV_TUNE("tt-ascalon-d8", tt_ascalon_d8, tt_ascalon_d8_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("xt-c908", generic, generic_ooo_tune_info) @@ -148,6 +149,10 @@ RISCV_CORE("xt-c920v2", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_" "xtheadsync", "xt-c920v2") +RISCV_CORE("tt-ascalon-x", "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_" + "zvfh_zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_" + "smstateen_ssaia_ssstrict_svadu", + "tt-ascalon-x") RISCV_CORE("tt-ascalon-d8", "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_" "zvfh_zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_" "smstateen_ssaia_ssstrict_svadu", diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi index f7b03a8f40f..ef9aeb96fcc 100644 --- a/gcc/doc/riscv-mcpu.texi +++ b/gcc/doc/riscv-mcpu.texi @@ -60,6 +60,8 @@ by particular CPU name. Permissible values for this option are: @samp{xt-c920v2}, +@samp{tt-ascalon-x}, + @samp{tt-ascalon-d8}, @samp{xiangshan-nanhu}, diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi index 6865bd6fbf7..e8de3bd0d29 100644 --- a/gcc/doc/riscv-mtune.texi +++ b/gcc/doc/riscv-mtune.texi @@ -30,6 +30,8 @@ particular CPU name. Permissible values for this option are: @samp{sifive-p600-series}, +@samp{tt-ascalon-x}, + @samp{tt-ascalon-d8}, @samp{thead-c906}, -- 2.43.0
