I had this sitting around waiting for stage1 to reopen before posting,
but I seemed to have lost track of it. I know GLIBC's riscv port does
preserve all callee-saved registers, but I'm unsure what all the other
libcs on riscv do, so for safety, I limited the usage to GLIBC.
I can drop that if everyone knows all riscv libcs act the same way.
This was regtested on riscv64-linux with no regressions.
Ok for trunk?
Peter
RISC-V: GLIBC's setjmp preserves callee-saved registers [PR87466]
gcc/
PR target/87466
* config/riscv/riscv.cc (TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P):
Define.
Signed-off-by: Peter Bergner <[email protected]>
---
gcc/config/riscv/riscv.cc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3be5606ba01..38e9306a5db 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -16383,6 +16383,11 @@ riscv_memtag_tag_bitsize ()
#undef TARGET_FNTYPE_ABI
#define TARGET_FNTYPE_ABI riscv_fntype_abi
+#if DEFAULT_LIBC == LIBC_GLIBC
+# undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
+# define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
+#endif
+
#undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
#define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
riscv_get_separate_components
--
2.43.0
