> Am 23.06.2026 um 19:24 schrieb Roger Sayle <[email protected]>:
>
>
> This is my attempt to tackle/workaround PR target/125855, a slowdown
> on AMD microarchitectures following my tweak to reduce the number of
> memory accesses (to load the sign-bit from the constant pool) for
> negation and absolute value on x86 when using SSE math.
>
> This patch optimizes the negation/abs of floating point values
> in memory, i.e. where the source and destination are the same
> memory location.
>
> As a motivating example:
>
> float x;
> void foo()
> {
> x = -x;
> }
>
> previously with -O2 generated:
>
> foo: movss x(%rip), %xmm0
> xorps .LC0(%rip), %xmm0
> movss %xmm0, x(%rip)
> ret
>
> with this patch, we instead generate:
>
> foo: xorb $-128, x+3(%rip)
Can we preserve the original memory access size? This should avoid STLF fails
for a subsequent load of the negated value.
Richard
> ret
>
> Less instructions, less memory transfers, less registers,
> less bytes (more store forwarding hazards for the hardware
> folks). This matches what LLVM does with similar code.
>
>
> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
> and make -k check, both with and without --target_board=unix{-m32}
> with no new failures. Ok for mainline?
>
>
> 2026-06-23 Roger Sayle <[email protected]>
>
> gcc/ChangeLog
> * config/i386/i386.md (*neg<MODEF>2_mem): New define_insn_and_split
> for negations with the same source and destination memory address.
> (*abs<MODEF>2_mem): Likewise for ABS.
> (*negabs<MODEF>2_mem): Likewise for NEG of ABS.
>
> gcc/testsuite/ChangeLog
> * gcc.target/i386/fabsneg-2.c: Update test case.
> * gcc.target/i386/fabsneg-3.c: New test case.
>
>
> Thanks in advance,
> Roger
> --
>
> <patchnm.txt>
