One simple way is extend the clobber list in the tlsdesc pattern, so
that we can prevent ra begin clobbered
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b90bfe0745a..11997692557 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2478,7 +2478,11 @@ (define_insn "@tlsdesc<mode>"
(unspec:P
[(match_operand:P 0 "symbolic_operand" "")]
UNSPEC_TLSDESC))
- (clobber (reg:P T0_REGNUM))]
+ (clobber (reg:P T0_REGNUM))
+ (clobber (reg:P VTYPE_REGNUM))
+ (clobber (reg:P VXRM_REGNUM))
+ (clobber (reg:P VXSAT_REGNUM))
+ (clobber (reg:P VL_REGNUM))]
"TARGET_TLSDESC"
{
return ".LT%=: auipc\ta0,%%tlsdesc_hi(%0)\;"
Luke Zhuang <[email protected]> 於 2026年6月24日週三 下午8:10寫道：
>
> Hi Andreas,
> I've fixed it in patch v2.
>
> Best,
> Luke Zhuang
>
> ------------------------------------------------------------------
> From:Andreas Schwab <[email protected]>
> Send Time:Tue, Jun 23, 2026, 17:33
> To:Luke Zhuang<[email protected]>
> CC:"gcc-patches"<[email protected]>;
> "kito.cheng"<[email protected]>; palmer<[email protected]>;
> "rdapp.gcc"<[email protected]>; andrew<[email protected]>;
> "jim.wilson.gcc"<[email protected]>;
> "juzhe.zhong"<[email protected]>; rdsandiford<[email protected]>;
> "zhuangzhi.zz"<[email protected]>
> Subject:Re: [PATCH] RISC-V: Declare TLSDESC clobbers for vector registers and
> CSRs per psABI
>
> On Jun 23 2026, Luke Zhuang wrote:
>
> > +/* Vector stores before and loads after the TLSDESC call. */
> > +/* { dg-final { scan-assembler-times {\tvs[0-9]+r\.v\t} 2 } } */
> > +/* { dg-final { scan-assembler-times {\tvl[0-9]+re[0-9]+\.v\t} 2 } } */
> > \ No newline at end of file
>
> Please fix the missing newline.
>
> --
> Andreas Schwab, SUSE Labs, [email protected]
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
