On 6/24/2026 9:19 AM, Luke Zhuang wrote:
Hi Kito,
Yes, as aarch64 did for SVE in <80c13ac5> (but they changed to
modeling like a real call later in <bb6ce448>). While for RISCV, we
have too many V registers, so the code maybe like:
(unspec:P [(match_operand:P 0 "symbolic_operand" "")]
UNSPEC_TLSDESC))
(clobber (reg:P T0_REGNUM))
(clobber (reg:P VTYPE_REGNUM))
(clobber (reg:P VXRM_REGNUM))
(clobber (reg:P VXSAT_REGNUM))
(clobber (reg:P VL_REGNUM))
(clobber (reg:RVVM1BI 96))
(clobber (reg:RVVM1BI 97))
(clobber (reg:RVVM1BI 98))
(clobber (reg:RVVM1BI 99))
(clobber (reg:RVVM1BI 100))
(clobber (reg:RVVM1BI 101))
(clobber (reg:RVVM1BI 102))
(clobber (reg:RVVM1BI 103))
(clobber (reg:RVVM1BI 104))
(clobber (reg:RVVM1BI 105))
(clobber (reg:RVVM1BI 106))
...
That looks too long, but yes I agree that's more precise. If that's
more preferable I can take this approach. May I ask what do you think?
So to keep the clobber list smaller, clobber v0, v8, v16, v24 using an
LMUL8 mode? Essentially every register you clobber this way covers 8
physical registers.
Jeff
