[PATCH v1 0/4] Add test for unsigned scalar SAT_MUL form 16-19

[pan2 . li]

From: Pan Li <pan2...@intel.com>

Those forms of unsigned scalar SAT_MUL from 16 to 19 are supported
in previous.  Thefore, add ut to make sure it works well.

Pan Li (4):
  RISC-V: Add testcase for unsigned scalar SAT_MUL form 16
  RISC-V: Add testcase for unsigned scalar SAT_MUL form 17
  RISC-V: Add testcase for unsigned scalar SAT_MUL form 18
  RISC-V: Add testcase for unsigned scalar SAT_MUL form 19

 .../gcc.target/riscv/sat/sat_arith.h          | 64 +++++++++++++++++++
 .../riscv/sat/sat_u_mul-17-u16-from-u128.c    | 11 ++++
 .../riscv/sat/sat_u_mul-17-u16-from-u32.c     | 11 ++++
 .../sat/sat_u_mul-17-u16-from-u64.rv32.c      | 11 ++++
 .../sat/sat_u_mul-17-u16-from-u64.rv64.c      | 11 ++++
 .../riscv/sat/sat_u_mul-17-u32-from-u128.c    | 11 ++++
 .../sat/sat_u_mul-17-u32-from-u64.rv32.c      | 11 ++++
 .../sat/sat_u_mul-17-u32-from-u64.rv64.c      | 11 ++++
 .../riscv/sat/sat_u_mul-17-u64-from-u128.c    | 11 ++++
 .../riscv/sat/sat_u_mul-17-u8-from-u128.c     | 11 ++++
 .../riscv/sat/sat_u_mul-17-u8-from-u16.c      | 11 ++++
 .../riscv/sat/sat_u_mul-17-u8-from-u32.c      | 11 ++++
 .../riscv/sat/sat_u_mul-17-u8-from-u64.rv32.c | 11 ++++
 .../riscv/sat/sat_u_mul-17-u8-from-u64.rv64.c | 11 ++++
 .../riscv/sat/sat_u_mul-18-u16-from-u128.c    | 11 ++++
 .../riscv/sat/sat_u_mul-18-u16-from-u32.c     | 11 ++++
 .../sat/sat_u_mul-18-u16-from-u64.rv32.c      | 11 ++++
 .../sat/sat_u_mul-18-u16-from-u64.rv64.c      | 11 ++++
 .../riscv/sat/sat_u_mul-18-u32-from-u128.c    | 11 ++++
 .../sat/sat_u_mul-18-u32-from-u64.rv32.c      | 11 ++++
 .../sat/sat_u_mul-18-u32-from-u64.rv64.c      | 11 ++++
 .../riscv/sat/sat_u_mul-18-u64-from-u128.c    | 11 ++++
 .../riscv/sat/sat_u_mul-18-u8-from-u128.c     | 11 ++++
 .../riscv/sat/sat_u_mul-18-u8-from-u16.c      | 11 ++++
 .../riscv/sat/sat_u_mul-18-u8-from-u32.c      | 11 ++++
 .../riscv/sat/sat_u_mul-18-u8-from-u64.rv32.c | 11 ++++
 .../riscv/sat/sat_u_mul-18-u8-from-u64.rv64.c | 11 ++++
 .../riscv/sat/sat_u_mul-19-u16-from-u128.c    | 11 ++++
 .../riscv/sat/sat_u_mul-19-u16-from-u32.c     | 11 ++++
 .../sat/sat_u_mul-19-u16-from-u64.rv32.c      | 11 ++++
 .../sat/sat_u_mul-19-u16-from-u64.rv64.c      | 11 ++++
 .../riscv/sat/sat_u_mul-19-u32-from-u128.c    | 11 ++++
 .../sat/sat_u_mul-19-u32-from-u64.rv32.c      | 11 ++++
 .../sat/sat_u_mul-19-u32-from-u64.rv64.c      | 11 ++++
 .../riscv/sat/sat_u_mul-19-u64-from-u128.c    | 11 ++++
 .../riscv/sat/sat_u_mul-19-u8-from-u128.c     | 11 ++++
 .../riscv/sat/sat_u_mul-19-u8-from-u16.c      | 11 ++++
 .../riscv/sat/sat_u_mul-19-u8-from-u32.c      | 11 ++++
 .../riscv/sat/sat_u_mul-19-u8-from-u64.rv32.c | 11 ++++
 .../riscv/sat/sat_u_mul-19-u8-from-u64.rv64.c | 11 ++++
 .../riscv/sat/sat_u_mul-20-u16-from-u128.c    | 11 ++++
 .../riscv/sat/sat_u_mul-20-u16-from-u32.c     | 11 ++++
 .../sat/sat_u_mul-20-u16-from-u64.rv32.c      | 11 ++++
 .../sat/sat_u_mul-20-u16-from-u64.rv64.c      | 11 ++++
 .../riscv/sat/sat_u_mul-20-u32-from-u128.c    | 11 ++++
 .../sat/sat_u_mul-20-u32-from-u64.rv32.c      | 11 ++++
 .../sat/sat_u_mul-20-u32-from-u64.rv64.c      | 11 ++++
 .../riscv/sat/sat_u_mul-20-u64-from-u128.c    | 11 ++++
 .../riscv/sat/sat_u_mul-20-u8-from-u128.c     | 11 ++++
 .../riscv/sat/sat_u_mul-20-u8-from-u16.c      | 11 ++++
 .../riscv/sat/sat_u_mul-20-u8-from-u32.c      | 11 ++++
 .../riscv/sat/sat_u_mul-20-u8-from-u64.rv32.c | 11 ++++
 .../riscv/sat/sat_u_mul-20-u8-from-u64.rv64.c | 11 ++++
 .../sat/sat_u_mul-run-17-u16-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-17-u16-from-u32.c | 16 +++++
 .../riscv/sat/sat_u_mul-run-17-u16-from-u64.c | 16 +++++
 .../sat/sat_u_mul-run-17-u32-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-17-u32-from-u64.c | 16 +++++
 .../sat/sat_u_mul-run-17-u64-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-17-u8-from-u128.c | 16 +++++
 .../riscv/sat/sat_u_mul-run-17-u8-from-u16.c  | 16 +++++
 .../riscv/sat/sat_u_mul-run-17-u8-from-u32.c  | 16 +++++
 .../riscv/sat/sat_u_mul-run-17-u8-from-u64.c  | 16 +++++
 .../sat/sat_u_mul-run-18-u16-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-18-u16-from-u32.c | 16 +++++
 .../riscv/sat/sat_u_mul-run-18-u16-from-u64.c | 16 +++++
 .../sat/sat_u_mul-run-18-u32-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-18-u32-from-u64.c | 16 +++++
 .../sat/sat_u_mul-run-18-u64-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-18-u8-from-u128.c | 16 +++++
 .../riscv/sat/sat_u_mul-run-18-u8-from-u16.c  | 16 +++++
 .../riscv/sat/sat_u_mul-run-18-u8-from-u32.c  | 16 +++++
 .../riscv/sat/sat_u_mul-run-18-u8-from-u64.c  | 16 +++++
 .../sat/sat_u_mul-run-19-u16-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-19-u16-from-u32.c | 16 +++++
 .../riscv/sat/sat_u_mul-run-19-u16-from-u64.c | 16 +++++
 .../sat/sat_u_mul-run-19-u32-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-19-u32-from-u64.c | 16 +++++
 .../sat/sat_u_mul-run-19-u64-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-19-u8-from-u128.c | 16 +++++
 .../riscv/sat/sat_u_mul-run-19-u8-from-u16.c  | 16 +++++
 .../riscv/sat/sat_u_mul-run-19-u8-from-u32.c  | 16 +++++
 .../riscv/sat/sat_u_mul-run-19-u8-from-u64.c  | 16 +++++
 .../sat/sat_u_mul-run-20-u16-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-20-u16-from-u32.c | 16 +++++
 .../riscv/sat/sat_u_mul-run-20-u16-from-u64.c | 16 +++++
 .../sat/sat_u_mul-run-20-u32-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-20-u32-from-u64.c | 16 +++++
 .../sat/sat_u_mul-run-20-u64-from-u128.c      | 16 +++++
 .../riscv/sat/sat_u_mul-run-20-u8-from-u128.c | 16 +++++
 .../riscv/sat/sat_u_mul-run-20-u8-from-u16.c  | 16 +++++
 .../riscv/sat/sat_u_mul-run-20-u8-from-u32.c  | 16 +++++
 .../riscv/sat/sat_u_mul-run-20-u8-from-u64.c  | 16 +++++
 93 files changed, 1276 insertions(+)
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gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-17-u16-from-u128.c
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gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-17-u16-from-u32.c
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gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-20-u8-from-u64.c

-- 
2.43.0