Hi Abhishek,
> On 23 Jun 2026, at 13:34, Abhishek Kaushik <[email protected]> wrote:
>
> This patch adds support for the following SME2p3/SVE2p3 x2 narrowing
> right shift intrinsics:
>
> * svqrshrn_s8_s16
> * svqrshrn_u8_u16
> * svqrshrun_u8_s16
> * svqshrn_s8_s16
> * svqshrn_s16_s32
> * svqshrn_u8_u16
> * svqshrn_u16_u32
> * svqshrun_u8_s16
> * svqshrun_u16_s32
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
> Define __ARM_FEATURE_SVE2p3 and __ARM_FEATURE_SME2p3.
> * config/aarch64/aarch64-sve-builtins-sve2.cc (svqshrn): New
> function.
> (svqshrun): Likewise.
> * config/aarch64/aarch64-sve-builtins-sve2.def: Add SVE2p3/SME2p3
> x2 narrowing right shift functions.
> * config/aarch64/aarch64-sve-builtins-sve2.h (svqshrn): Declare.
> (svqshrun): Likewise.
> * config/aarch64/aarch64-sve-builtins.cc
> (TYPES_qshr_x2_sve2p3): New macro.
> (TYPES_qrshr_x2_sve2p3): Likewise.
> (TYPES_qshru_x2_sve2p3): Likewise.
> (TYPES_qrshrun_x2_sve2p3): Likewise.
> (qshr_x2_sve2p3): New types array.
> (qrshr_x2_sve2p3): Likewise.
> (qrshrun_x2_sve2p3): Likewise.
> (qshru_x2_sve2p3): Likewise.
> * config/aarch64/aarch64-sve2.md: Document SVE2p3/SME2p3
> narrowing right shifts.
> (@aarch64_sve_<sve_int_op><mode>): New define_insn.
> * config/aarch64/aarch64.h (TARGET_SVE2p3): Define.
> (TARGET_SME2p3): Likewise.
> (TARGET_STREAMING_SME2p3): Likewise.
> (TARGET_SVE2p3_OR_SME2p3): Likewise.
> * config/aarch64/iterators.md (SVE_FULL_HIx2): New mode iterator.
> (UNSPEC_SQSHRN): New unspec.
> (UNSPEC_SQSHRUN): Likewise.
> (UNSPEC_UQSHRN): Likewise.
> (VNARROW): Add VNx16HI.
> (Ventype): Likewise.
> (SVE2_INT_SHIFT_IMM_NARROWxN): Add SQSHRN, SQSHRUN and UQSHRN.
> (sve_int_op): Add names for UNSPEC_SQSHRN, UNSPEC_SQSHRUN and
> UNSPEC_UQSHRN.
>
> gcc/testsuite/ChangeLog:
>
This is missing the lib/target-supports.exp changes.
> * gcc.target/aarch64/sme2/acle-asm/qrshrn_s8_x2.c: New test.
> * gcc.target/aarch64/sme2/acle-asm/qrshrn_u8_x2.c: Likewise.
> * gcc.target/aarch64/sme2/acle-asm/qrshrun_u8_x2.c: Likewise.
> * gcc.target/aarch64/sme2/acle-asm/qshrn_s16_x2.c: Likewise.
> * gcc.target/aarch64/sme2/acle-asm/qshrn_s8_x2.c: Likewise.
> * gcc.target/aarch64/sme2/acle-asm/qshrn_u16_x2.c: Likewise.
> * gcc.target/aarch64/sme2/acle-asm/qshrn_u8_x2.c: Likewise.
> * gcc.target/aarch64/sme2/acle-asm/qshrun_u16_x2.c: Likewise.
> * gcc.target/aarch64/sme2/acle-asm/qshrun_u8_x2.c: Likewise.
> ---
> gcc/config/aarch64/aarch64-c.cc | 2 +
> .../aarch64/aarch64-sve-builtins-sve2.cc | 3 ++
> .../aarch64/aarch64-sve-builtins-sve2.def | 7 +++
> .../aarch64/aarch64-sve-builtins-sve2.h | 2 +
> gcc/config/aarch64/aarch64-sve-builtins.cc | 30 +++++++++++
> gcc/config/aarch64/aarch64-sve2.md | 14 +++++
> gcc/config/aarch64/aarch64.h | 8 +++
> gcc/config/aarch64/iterators.md | 14 ++++-
> .../aarch64/sme2/acle-asm/qrshrn_s8_x2.c | 53 +++++++++++++++++++
> .../aarch64/sme2/acle-asm/qrshrn_u8_x2.c | 53 +++++++++++++++++++
> .../aarch64/sme2/acle-asm/qrshrun_u8_x2.c | 53 +++++++++++++++++++
> .../aarch64/sme2/acle-asm/qshrn_s16_x2.c | 53 +++++++++++++++++++
> .../aarch64/sme2/acle-asm/qshrn_s8_x2.c | 53 +++++++++++++++++++
> .../aarch64/sme2/acle-asm/qshrn_u16_x2.c | 53 +++++++++++++++++++
> .../aarch64/sme2/acle-asm/qshrn_u8_x2.c | 53 +++++++++++++++++++
> .../aarch64/sme2/acle-asm/qshrun_u16_x2.c | 53 +++++++++++++++++++
> .../aarch64/sme2/acle-asm/qshrun_u8_x2.c | 53 +++++++++++++++++++
> gcc/testsuite/lib/target-supports.exp | 4 +-
> 18 files changed, 558 insertions(+), 3 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrn_s8_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrn_u8_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrun_u8_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_s16_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_s8_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_u16_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_u8_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrun_u16_x2.c
> create mode 100644
> gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrun_u8_x2.c
>
> diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
> index e11cf95a08a..cad0e530eef 100644
> --- a/gcc/config/aarch64/aarch64-c.cc
> +++ b/gcc/config/aarch64/aarch64-c.cc
> @@ -236,6 +236,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
> aarch64_def_or_undef (TARGET_SVE2_SM4, "__ARM_FEATURE_SVE2_SM4", pfile);
> aarch64_def_or_undef (TARGET_SVE2p1, "__ARM_FEATURE_SVE2p1", pfile);
> aarch64_def_or_undef (TARGET_SVE2p2, "__ARM_FEATURE_SVE2p2", pfile);
> + aarch64_def_or_undef (TARGET_SVE2p3, "__ARM_FEATURE_SVE2p3", pfile);
>
> aarch64_def_or_undef (TARGET_LSE, "__ARM_FEATURE_ATOMICS", pfile);
> aarch64_def_or_undef (TARGET_AES, "__ARM_FEATURE_AES", pfile);
> @@ -315,6 +316,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
> aarch64_def_or_undef (AARCH64_HAVE_ISA (SME2p1),
> "__ARM_FEATURE_SME2p1", pfile);
> aarch64_def_or_undef (TARGET_SME2p2, "__ARM_FEATURE_SME2p2", pfile);
> + aarch64_def_or_undef (TARGET_SME2p3, "__ARM_FEATURE_SME2p3", pfile);
> aarch64_def_or_undef (TARGET_FAMINMAX, "__ARM_FEATURE_FAMINMAX", pfile);
> aarch64_def_or_undef (TARGET_PCDPHINT, "__ARM_FEATURE_PCDPHINT", pfile);
> aarch64_def_or_undef (AARCH64_HAVE_ISA (SSVE_FEXPA),
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
> b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
> index 5ea08056ae3..ceb6be97f67 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc
> @@ -1218,6 +1218,9 @@ FUNCTION (svqrshr, unspec_based_uncond_function,
> (UNSPEC_SQRSHR,
> UNSPEC_UQRSHR, -1, -1, 1))
> FUNCTION (svqrshrn, unspec_based_uncond_function, (UNSPEC_SQRSHRN,
> UNSPEC_UQRSHRN, -1, -1, 1))
> +FUNCTION (svqshrn, unspec_based_uncond_function, (UNSPEC_SQSHRN,
> + UNSPEC_UQSHRN, -1, -1, 1))
> +FUNCTION (svqshrun, unspec_based_uncond_function, (UNSPEC_SQSHRUN, -1, -1,
> -1, 1))
> FUNCTION (svqrshrnb, unspec_based_function, (UNSPEC_SQRSHRNB,
> UNSPEC_UQRSHRNB, -1))
> FUNCTION (svqrshrnt, unspec_based_function, (UNSPEC_SQRSHRNT,
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
> b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
> index 1a55de890cf..c90c5486f1f 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
> @@ -315,6 +315,13 @@ DEF_SVE_FUNCTION (svrint64x, unary, sd_float, mxz)
> DEF_SVE_FUNCTION (svrint64z, unary, sd_float, mxz)
> #undef REQUIRED_EXTENSIONS
>
> +#define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2p3,
> AARCH64_FL_SME2p3)
> +DEF_SVE_FUNCTION_GS (svqrshrn, shift_right_imm_narrowxn, qrshr_x2_sve2p3,
> x2, none)
> +DEF_SVE_FUNCTION_GS (svqrshrun, shift_right_imm_narrowxn, qrshrun_x2_sve2p3,
> x2, none)
> +DEF_SVE_FUNCTION_GS (svqshrn, shift_right_imm_narrowxn, qshr_x2_sve2p3, x2,
> none)
> +DEF_SVE_FUNCTION_GS (svqshrun, shift_right_imm_narrowxn, qshru_x2_sve2p3,
> x2, none)
> +#undef REQUIRED_EXTENSIONS
> +
> #define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2)
> DEF_SVE_FUNCTION_GS (svadd, binary_single, all_integer, x24, none)
> DEF_SVE_FUNCTION_GS (svclamp, clamp, all_arith, x24, none)
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
> b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
> index b2f2698b880..64b44dce7a8 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h
> @@ -175,6 +175,8 @@ namespace aarch64_sve
> extern const function_base *const svqrdmulh_lane;
> extern const function_base *const svqrshl;
> extern const function_base *const svqrshr;
> + extern const function_base *const svqshrn;
> + extern const function_base *const svqshrun;
> extern const function_base *const svqrshrn;
> extern const function_base *const svqrshrnb;
> extern const function_base *const svqrshrnt;
> diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc
> b/gcc/config/aarch64/aarch64-sve-builtins.cc
> index cd78713440f..5fa3d7c4c03 100644
> --- a/gcc/config/aarch64/aarch64-sve-builtins.cc
> +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc
> @@ -553,10 +553,36 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {
> D (s16, s32), \
> D (u16, u32)
>
> +/* _s8_s16
> + _u8_u16
> + _s16_s32
> + _u16_u32. */
> +#define TYPES_qshr_x2_sve2p3(S, D, T) \
> + D (s8, s16), \
> + D (u8, u16), \
> + D (s16, s32), \
> + D (u16, u32)
> +
> +/* _s8_s16
> + _u8_u16. */
> +#define TYPES_qrshr_x2_sve2p3(S, D, T) \
> + D (s8, s16), \
> + D (u8, u16)
> +
> /* _u16_s32. */
> #define TYPES_qrshru_x2(S, D, T) \
> D (u16, s32)
>
> +/* _u8_s16
> + _16_s32. */
Should say _u16_s32 ?
> +#define TYPES_qshru_x2_sve2p3(S, D, T) \
> + D (u8, s16), \
> + D (u16, s32)
> +
> +/* _u8_s16. */
> +#define TYPES_qrshrun_x2_sve2p3(S, D, T) \
> + D (u8, s16)
> +
> /* _s8_s32
> _s16_s64
> _u8_u32
> @@ -858,9 +884,13 @@ DEF_SVE_TYPES_ARRAY (cvtnx_mf8);
> DEF_SVE_TYPES_ARRAY (inc_dec_n);
> DEF_SVE_TYPES_ARRAY (qcvt_x2);
> DEF_SVE_TYPES_ARRAY (qcvt_x4);
> +DEF_SVE_TYPES_ARRAY (qshr_x2_sve2p3);
> DEF_SVE_TYPES_ARRAY (qrshr_x2);
> +DEF_SVE_TYPES_ARRAY (qrshr_x2_sve2p3);
> DEF_SVE_TYPES_ARRAY (qrshr_x4);
> DEF_SVE_TYPES_ARRAY (qrshru_x2);
> +DEF_SVE_TYPES_ARRAY (qrshrun_x2_sve2p3);
> +DEF_SVE_TYPES_ARRAY (qshru_x2_sve2p3);
> DEF_SVE_TYPES_ARRAY (qrshru_x4);
> DEF_SVE_TYPES_ARRAY (reinterpret);
> DEF_SVE_TYPES_ARRAY (reinterpret_b);
> diff --git a/gcc/config/aarch64/aarch64-sve2.md
> b/gcc/config/aarch64/aarch64-sve2.md
> index 1d428619c07..ae6d85f5ef3 100644
> --- a/gcc/config/aarch64/aarch64-sve2.md
> +++ b/gcc/config/aarch64/aarch64-sve2.md
> @@ -3165,10 +3165,13 @@
> ;; ---- [INT] Multi-vector narrowing right shifts
> ;; -------------------------------------------------------------------------
> ;; Includes:
> +;; - SQSHRN (SVE2p3, SME2p3)
> +;; - SQSHRUN (SVE2p3, SME2p3)
> ;; - SQRSHR (SME2)
> ;; - SQRSHRN (SVE2p1, SME2)
> ;; - SQRSHRU (SME2)
> ;; - SQRSHRUN (SVE2p1, SME2)
> +;; - UQSHRN (SVE2p3, SME2p3)
> ;; - UQRSHR (SME2)
> ;; - UQRSHRN (SVE2p1, SME2)
> ;; -------------------------------------------------------------------------
> @@ -3184,6 +3187,17 @@
> [(set_attr "sve_type" "sve_int_shift")]
> )
>
> +(define_insn "@aarch64_sve_<sve_int_op><mode>"
> + [(set (match_operand:<VNARROW> 0 "register_operand" "=w")
> + (unspec:<VNARROW>
> + [(match_operand:SVE_FULL_HIx2 1 "register_operand" "Uw<vector_count>")
> + (match_operand:DI 2 "const_int_operand")]
> + SVE2_INT_SHIFT_IMM_NARROWxN))]
> + "TARGET_SVE2p3_OR_SME2p3"
> + "<sve_int_op>\t%0.<Ventype>, %1, #%2"
> + [(set_attr "sve_type" "sve_int_shift")]
> +)
> +
> ;; =========================================================================
> ;; == Pairwise arithmetic
> ;; =========================================================================
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index c3c61c6939c..4d8b45e2871 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -318,6 +318,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE
> ATTRIBUTE_UNUSED
> /* SVE2p2 instructions, enabled through +sve2p2. */
> #define TARGET_SVE2p2 AARCH64_HAVE_ISA (SVE2p2)
>
> +#define TARGET_SVE2p3 AARCH64_HAVE_ISA (SVE2p3)
> +
> /* SME instructions, enabled through +sme. Note that this does not
> imply anything about the state of PSTATE.SM; instructions that require
> SME and streaming mode should use TARGET_STREAMING instead. */
> @@ -351,6 +353,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE
> ATTRIBUTE_UNUSED
> /* SME2p2 instructions, enabled through +sme2p2. */
> #define TARGET_SME2p2 AARCH64_HAVE_ISA (SME2p2)
>
> +#define TARGET_SME2p3 AARCH64_HAVE_ISA (SME2p3)
> +
> /* Same with streaming mode enabled. */
> #define TARGET_STREAMING_SME2 (TARGET_STREAMING && TARGET_SME2)
>
> @@ -358,6 +362,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE
> ATTRIBUTE_UNUSED
>
> #define TARGET_STREAMING_SME2p2 (TARGET_STREAMING && AARCH64_HAVE_ISA
> (SME2p2))
>
> +#define TARGET_STREAMING_SME2p3 (TARGET_STREAMING && AARCH64_HAVE_ISA
> (SME2p3))
This define is not used anywhere, shouldn’t it be used somehow as part of the
definition of...
> +
> #define TARGET_SME_B16B16 AARCH64_HAVE_ISA (SME_B16B16)
>
> /* ARMv8.3-A features. */
> @@ -532,6 +538,8 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE
> ATTRIBUTE_UNUSED
> functions, since streaming mode itself implies SME. */
> #define TARGET_SVE2p1_OR_SME (TARGET_SVE2p1 || TARGET_STREAMING)
>
> +#define TARGET_SVE2p3_OR_SME2p3 (TARGET_SVE2p3 || TARGET_SME2p3)
… this?
> +
> #define TARGET_SVE2p1_OR_SME2 \
> ((TARGET_SVE2p1 || TARGET_STREAMING) \
> && (TARGET_SME2 || TARGET_NON_STREAMING))
> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
> index 2d1522a348a..05a8d654c43 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -623,6 +623,8 @@
> ;; 2x and 4x tuples of the above, excluding 2x DI.
> (define_mode_iterator SVE_FULL_SIx2_SDIx4 [VNx8SI VNx16SI VNx8DI])
>
> +(define_mode_iterator SVE_FULL_HIx2 [VNx16HI])
> +
> ;; Fully-packed SVE floating-point vector modes that have 32-bit or 64-bit
> ;; elements.
> (define_mode_iterator SVE_FULL_SDF [VNx4SF VNx2DF])
> @@ -1200,6 +1202,8 @@
> UNSPEC_SQRDCMLAH270 ; Used in aarch64-sve2.md.
> UNSPEC_SQRDCMLAH90 ; Used in aarch64-sve2.md.
> UNSPEC_SQRSHR ; Used in aarch64-sve2.md.
> + UNSPEC_SQSHRN ; Used in aarch64-sve2.md.
> + UNSPEC_SQSHRUN ; Used in aarch64-sve2.md.
> UNSPEC_SQRSHRN ; Used in aarch64-sve2.md.
> UNSPEC_SQRSHRNB ; Used in aarch64-sve2.md.
> UNSPEC_SQRSHRNT ; Used in aarch64-sve2.md.
> @@ -1243,6 +1247,7 @@
> UNSPEC_UMULLB ; Used in aarch64-sve2.md.
> UNSPEC_UMULLT ; Used in aarch64-sve2.md.
> UNSPEC_UQRSHR ; Used in aarch64-sve2.md.
> + UNSPEC_UQSHRN ; Used in aarch64-sve2.md.
> UNSPEC_UQRSHRN ; Used in aarch64-sve2.md.
> UNSPEC_UQRSHRNB ; Used in aarch64-sve2.md.
> UNSPEC_UQRSHRNT ; Used in aarch64-sve2.md.
> @@ -2138,7 +2143,7 @@
> (VNx4SI "VNx8HI") (VNx4SF "VNx8HF")
> (VNx2DI "VNx4SI") (VNx2DF "VNx4SF")
> (VNx8SI "VNx8HI") (VNx16SI "VNx16QI")
> - (VNx8DI "VNx8HI")])
> + (VNx8DI "VNx8HI") (VNx16HI "VNx16QI")])
> (define_mode_attr Vnarrow [(VNx8HI "vnx16qi")
> (VNx4SI "vnx8hi") (VNx4SF "vnx8hf")
> (VNx2DI "vnx4si") (VNx2DF "vnx4sf")
> @@ -2276,6 +2281,7 @@
>
> ;; SVE vector after narrowing.
> (define_mode_attr Ventype [(VNx8HI "b")
> + (VNx16HI "b")
> (VNx4SI "h") (VNx4SF "h")
> (VNx2DI "s") (VNx2DF "s")
> (VNx8SI "h") (VNx16SI "b")
> @@ -4045,10 +4051,13 @@
>
> (define_int_iterator SVE2_INT_SHIFT_IMM_NARROWxN
> [(UNSPEC_SQRSHR "TARGET_STREAMING_SME2")
> + (UNSPEC_SQSHRN "TARGET_SVE2p3_OR_SME2p3")
> + (UNSPEC_SQSHRUN "TARGET_SVE2p3_OR_SME2p3")
> (UNSPEC_SQRSHRN "TARGET_SVE2p1_OR_SME2")
> (UNSPEC_SQRSHRU "TARGET_STREAMING_SME2")
> (UNSPEC_SQRSHRUN "TARGET_SVE2p1_OR_SME2")
> (UNSPEC_UQRSHR "TARGET_STREAMING_SME2")
> + (UNSPEC_UQSHRN "TARGET_SVE2p3_OR_SME2p3")
> (UNSPEC_UQRSHRN "TARGET_SVE2p1_OR_SME2")])
>
> (define_int_iterator SVE2_INT_SHIFT_INSERT [UNSPEC_SLI UNSPEC_SRI])
> @@ -4939,6 +4948,8 @@
> (UNSPEC_SQRDMULH "sqrdmulh")
> (UNSPEC_SQRSHL "sqrshl")
> (UNSPEC_SQRSHR "sqrshr")
> + (UNSPEC_SQSHRN "sqshrn")
> + (UNSPEC_SQSHRUN "sqshrun")
> (UNSPEC_SQRSHRN "sqrshrn")
> (UNSPEC_SQRSHRNB "sqrshrnb")
> (UNSPEC_SQRSHRNT "sqrshrnt")
> @@ -4989,6 +5000,7 @@
> (UNSPEC_UMULLT "umullt")
> (UNSPEC_UQRSHL "uqrshl")
> (UNSPEC_UQRSHR "uqrshr")
> + (UNSPEC_UQSHRN "uqshrn")
> (UNSPEC_UQRSHRN "uqrshrn")
> (UNSPEC_UQRSHRNB "uqrshrnb")
> (UNSPEC_UQRSHRNT "uqrshrnt")
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrn_s8_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrn_s8_x2.c
> new file mode 100644
> index 00000000000..049db7d8690
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrn_s8_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qrshrn_z0_z0_1:
> +** sqrshrn z0\.b, {z0\.h - z1\.h}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z0_z0_1, svint16x2_t, svint8_t,
> + z0_res = svqrshrn_n_s8_s16_x2 (z0, 1),
> + z0_res = svqrshrn_s8 (z0, 1))
> +
> +/*
> +** qrshrn_z0_z6_8:
> +** sqrshrn z0\.b, {z6\.h - z7\.h}, #8
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z0_z6_8, svint16x2_t, svint8_t,
> + z0_res = svqrshrn_n_s8_s16_x2 (z6, 8),
> + z0_res = svqrshrn_s8 (z6, 8))
> +
> +/*
> +** qrshrn_z0_z29_5:
> +** mov [^\n]+
> +** mov [^\n]+
> +** sqrshrn z0\.b, [^\n]+, #5
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z0_z29_5, svint16x2_t, svint8_t,
> + z0_res = svqrshrn_n_s8_s16_x2 (z29, 5),
> + z0_res = svqrshrn_s8 (z29, 5))
> +
> +/*
> +** qrshrn_z5_z0_3:
> +** sqrshrn z5\.b, {z0\.h - z1\.h}, #3
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z5_z0_3, svint16x2_t, svint8_t,
> + z5 = svqrshrn_n_s8_s16_x2 (z0, 3),
> + z5 = svqrshrn_s8 (z0, 3))
> +
> +/*
> +** qrshrn_z22_z16_7:
> +** sqrshrn z22\.b, {z16\.h - z17\.h}, #7
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z22_z16_7, svint16x2_t, svint8_t,
> + z22 = svqrshrn_n_s8_s16_x2 (z16, 7),
> + z22 = svqrshrn_s8 (z16, 7))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrn_u8_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrn_u8_x2.c
> new file mode 100644
> index 00000000000..974deec9fe3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrn_u8_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qrshrn_z0_z0_1:
> +** uqrshrn z0\.b, {z0\.h - z1\.h}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z0_z0_1, svuint16x2_t, svuint8_t,
> + z0_res = svqrshrn_n_u8_u16_x2 (z0, 1),
> + z0_res = svqrshrn_u8 (z0, 1))
> +
> +/*
> +** qrshrn_z0_z6_8:
> +** uqrshrn z0\.b, {z6\.h - z7\.h}, #8
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z0_z6_8, svuint16x2_t, svuint8_t,
> + z0_res = svqrshrn_n_u8_u16_x2 (z6, 8),
> + z0_res = svqrshrn_u8 (z6, 8))
> +
> +/*
> +** qrshrn_z0_z29_5:
> +** mov [^\n]+
> +** mov [^\n]+
> +** uqrshrn z0\.b, [^\n]+, #5
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z0_z29_5, svuint16x2_t, svuint8_t,
> + z0_res = svqrshrn_n_u8_u16_x2 (z29, 5),
> + z0_res = svqrshrn_u8 (z29, 5))
> +
> +/*
> +** qrshrn_z5_z0_3:
> +** uqrshrn z5\.b, {z0\.h - z1\.h}, #3
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z5_z0_3, svuint16x2_t, svuint8_t,
> + z5 = svqrshrn_n_u8_u16_x2 (z0, 3),
> + z5 = svqrshrn_u8 (z0, 3))
> +
> +/*
> +** qrshrn_z22_z16_7:
> +** uqrshrn z22\.b, {z16\.h - z17\.h}, #7
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrn_z22_z16_7, svuint16x2_t, svuint8_t,
> + z22 = svqrshrn_n_u8_u16_x2 (z16, 7),
> + z22 = svqrshrn_u8 (z16, 7))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrun_u8_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrun_u8_x2.c
> new file mode 100644
> index 00000000000..8834c38a160
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qrshrun_u8_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qrshrun_z0_z0_1:
> +** sqrshrun z0\.b, {z0\.h - z1\.h}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrun_z0_z0_1, svint16x2_t, svuint8_t,
> + z0_res = svqrshrun_n_u8_s16_x2 (z0, 1),
> + z0_res = svqrshrun_u8 (z0, 1))
> +
> +/*
> +** qrshrun_z0_z6_8:
> +** sqrshrun z0\.b, {z6\.h - z7\.h}, #8
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrun_z0_z6_8, svint16x2_t, svuint8_t,
> + z0_res = svqrshrun_n_u8_s16_x2 (z6, 8),
> + z0_res = svqrshrun_u8 (z6, 8))
> +
> +/*
> +** qrshrun_z0_z29_5:
> +** mov [^\n]+
> +** mov [^\n]+
> +** sqrshrun z0\.b, [^\n]+, #5
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrun_z0_z29_5, svint16x2_t, svuint8_t,
> + z0_res = svqrshrun_n_u8_s16_x2 (z29, 5),
> + z0_res = svqrshrun_u8 (z29, 5))
> +
> +/*
> +** qrshrun_z5_z0_3:
> +** sqrshrun z5\.b, {z0\.h - z1\.h}, #3
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrun_z5_z0_3, svint16x2_t, svuint8_t,
> + z5 = svqrshrun_n_u8_s16_x2 (z0, 3),
> + z5 = svqrshrun_u8 (z0, 3))
> +
> +/*
> +** qrshrun_z22_z16_7:
> +** sqrshrun z22\.b, {z16\.h - z17\.h}, #7
> +** ret
> +*/
> +TEST_X2_NARROW (qrshrun_z22_z16_7, svint16x2_t, svuint8_t,
> + z22 = svqrshrun_n_u8_s16_x2 (z16, 7),
> + z22 = svqrshrun_u8 (z16, 7))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_s16_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_s16_x2.c
> new file mode 100644
> index 00000000000..fcfc7d3c55c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_s16_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qshrn_z0_z0_1:
> +** sqshrn z0\.h, {z0\.s - z1\.s}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z0_1, svint32x2_t, svint16_t,
> + z0_res = svqshrn_n_s16_s32_x2 (z0, 1),
> + z0_res = svqshrn_s16 (z0, 1))
> +
> +/*
> +** qshrn_z0_z6_16:
> +** sqshrn z0\.h, {z6\.s - z7\.s}, #16
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z6_16, svint32x2_t, svint16_t,
> + z0_res = svqshrn_n_s16_s32_x2 (z6, 16),
> + z0_res = svqshrn_s16 (z6, 16))
> +
> +/*
> +** qshrn_z0_z29_13:
> +** mov [^\n]+
> +** mov [^\n]+
> +** sqshrn z0\.h, [^\n]+, #13
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z29_13, svint32x2_t, svint16_t,
> + z0_res = svqshrn_n_s16_s32_x2 (z29, 13),
> + z0_res = svqshrn_s16 (z29, 13))
> +
> +/*
> +** qshrn_z5_z0_11:
> +** sqshrn z5\.h, {z0\.s - z1\.s}, #11
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z5_z0_11, svint32x2_t, svint16_t,
> + z5 = svqshrn_n_s16_s32_x2 (z0, 11),
> + z5 = svqshrn_s16 (z0, 11))
> +
> +/*
> +** qshrn_z22_z16_15:
> +** sqshrn z22\.h, {z16\.s - z17\.s}, #15
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z22_z16_15, svint32x2_t, svint16_t,
> + z22 = svqshrn_n_s16_s32_x2 (z16, 15),
> + z22 = svqshrn_s16 (z16, 15))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_s8_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_s8_x2.c
> new file mode 100644
> index 00000000000..c006bbcff56
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_s8_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qshrn_z0_z0_1:
> +** sqshrn z0\.b, {z0\.h - z1\.h}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z0_1, svint16x2_t, svint8_t,
> + z0_res = svqshrn_n_s8_s16_x2 (z0, 1),
> + z0_res = svqshrn_s8 (z0, 1))
> +
> +/*
> +** qshrn_z0_z6_8:
> +** sqshrn z0\.b, {z6\.h - z7\.h}, #8
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z6_8, svint16x2_t, svint8_t,
> + z0_res = svqshrn_n_s8_s16_x2 (z6, 8),
> + z0_res = svqshrn_s8 (z6, 8))
> +
> +/*
> +** qshrn_z0_z29_5:
> +** mov [^\n]+
> +** mov [^\n]+
> +** sqshrn z0\.b, [^\n]+, #5
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z29_5, svint16x2_t, svint8_t,
> + z0_res = svqshrn_n_s8_s16_x2 (z29, 5),
> + z0_res = svqshrn_s8 (z29, 5))
> +
> +/*
> +** qshrn_z5_z0_3:
> +** sqshrn z5\.b, {z0\.h - z1\.h}, #3
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z5_z0_3, svint16x2_t, svint8_t,
> + z5 = svqshrn_n_s8_s16_x2 (z0, 3),
> + z5 = svqshrn_s8 (z0, 3))
> +
> +/*
> +** qshrn_z22_z16_7:
> +** sqshrn z22\.b, {z16\.h - z17\.h}, #7
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z22_z16_7, svint16x2_t, svint8_t,
> + z22 = svqshrn_n_s8_s16_x2 (z16, 7),
> + z22 = svqshrn_s8 (z16, 7))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_u16_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_u16_x2.c
> new file mode 100644
> index 00000000000..a0e6df45ca6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_u16_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qshrn_z0_z0_1:
> +** uqshrn z0\.h, {z0\.s - z1\.s}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z0_1, svuint32x2_t, svuint16_t,
> + z0_res = svqshrn_n_u16_u32_x2 (z0, 1),
> + z0_res = svqshrn_u16 (z0, 1))
> +
> +/*
> +** qshrn_z0_z6_16:
> +** uqshrn z0\.h, {z6\.s - z7\.s}, #16
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z6_16, svuint32x2_t, svuint16_t,
> + z0_res = svqshrn_n_u16_u32_x2 (z6, 16),
> + z0_res = svqshrn_u16 (z6, 16))
> +
> +/*
> +** qshrn_z0_z29_13:
> +** mov [^\n]+
> +** mov [^\n]+
> +** uqshrn z0\.h, [^\n]+, #13
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z29_13, svuint32x2_t, svuint16_t,
> + z0_res = svqshrn_n_u16_u32_x2 (z29, 13),
> + z0_res = svqshrn_u16 (z29, 13))
> +
> +/*
> +** qshrn_z5_z0_11:
> +** uqshrn z5\.h, {z0\.s - z1\.s}, #11
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z5_z0_11, svuint32x2_t, svuint16_t,
> + z5 = svqshrn_n_u16_u32_x2 (z0, 11),
> + z5 = svqshrn_u16 (z0, 11))
> +
> +/*
> +** qshrn_z22_z16_15:
> +** uqshrn z22\.h, {z16\.s - z17\.s}, #15
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z22_z16_15, svuint32x2_t, svuint16_t,
> + z22 = svqshrn_n_u16_u32_x2 (z16, 15),
> + z22 = svqshrn_u16 (z16, 15))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_u8_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_u8_x2.c
> new file mode 100644
> index 00000000000..f74e76c9f9d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrn_u8_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qshrn_z0_z0_1:
> +** uqshrn z0\.b, {z0\.h - z1\.h}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z0_1, svuint16x2_t, svuint8_t,
> + z0_res = svqshrn_n_u8_u16_x2 (z0, 1),
> + z0_res = svqshrn_u8 (z0, 1))
> +
> +/*
> +** qshrn_z0_z6_8:
> +** uqshrn z0\.b, {z6\.h - z7\.h}, #8
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z6_8, svuint16x2_t, svuint8_t,
> + z0_res = svqshrn_n_u8_u16_x2 (z6, 8),
> + z0_res = svqshrn_u8 (z6, 8))
> +
> +/*
> +** qshrn_z0_z29_5:
> +** mov [^\n]+
> +** mov [^\n]+
> +** uqshrn z0\.b, [^\n]+, #5
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z29_5, svuint16x2_t, svuint8_t,
> + z0_res = svqshrn_n_u8_u16_x2 (z29, 5),
> + z0_res = svqshrn_u8 (z29, 5))
> +
> +/*
> +** qshrn_z5_z0_3:
> +** uqshrn z5\.b, {z0\.h - z1\.h}, #3
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z5_z0_3, svuint16x2_t, svuint8_t,
> + z5 = svqshrn_n_u8_u16_x2 (z0, 3),
> + z5 = svqshrn_u8 (z0, 3))
> +
> +/*
> +** qshrn_z22_z16_7:
> +** uqshrn z22\.b, {z16\.h - z17\.h}, #7
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z22_z16_7, svuint16x2_t, svuint8_t,
> + z22 = svqshrn_n_u8_u16_x2 (z16, 7),
> + z22 = svqshrn_u8 (z16, 7))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrun_u16_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrun_u16_x2.c
> new file mode 100644
> index 00000000000..72e0ff3419c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrun_u16_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qshrn_z0_z0_1:
> +** sqshrun z0\.h, {z0\.s - z1\.s}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z0_1, svint32x2_t, svuint16_t,
> + z0_res = svqshrun_n_u16_s32_x2 (z0, 1),
> + z0_res = svqshrun_u16 (z0, 1))
> +
> +/*
> +** qshrn_z0_z6_16:
> +** sqshrun z0\.h, {z6\.s - z7\.s}, #16
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z6_16, svint32x2_t, svuint16_t,
> + z0_res = svqshrun_n_u16_s32_x2 (z6, 16),
> + z0_res = svqshrun_u16 (z6, 16))
> +
> +/*
> +** qshrn_z0_z29_13:
> +** mov [^\n]+
> +** mov [^\n]+
> +** sqshrun z0\.h, [^\n]+, #13
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z29_13, svint32x2_t, svuint16_t,
> + z0_res = svqshrun_n_u16_s32_x2 (z29, 13),
> + z0_res = svqshrun_u16 (z29, 13))
> +
> +/*
> +** qshrn_z5_z0_11:
> +** sqshrun z5\.h, {z0\.s - z1\.s}, #11
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z5_z0_11, svint32x2_t, svuint16_t,
> + z5 = svqshrun_n_u16_s32_x2 (z0, 11),
> + z5 = svqshrun_u16 (z0, 11))
> +
> +/*
> +** qshrn_z22_z16_15:
> +** sqshrun z22\.h, {z16\.s - z17\.s}, #15
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z22_z16_15, svint32x2_t, svuint16_t,
> + z22 = svqshrun_n_u16_s32_x2 (z16, 15),
> + z22 = svqshrun_u16 (z16, 15))
> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrun_u8_x2.c
> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrun_u8_x2.c
> new file mode 100644
> index 00000000000..74255dcb137
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/qshrun_u8_x2.c
> @@ -0,0 +1,53 @@
> +/* { dg-do assemble { target aarch64_asm_sme2p3_ok } } */
> +/* { dg-do compile { target { ! aarch64_asm_sme2p3_ok } } } */
> +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
> +
> +#include "test_sme2_acle.h"
> +#pragma GCC target "+sme2p3"
> +
> +/*
> +** qshrn_z0_z0_1:
> +** sqshrun z0\.b, {z0\.h - z1\.h}, #1
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z0_1, svint16x2_t, svuint8_t,
Minor nit, but these functions should be named qshrun to be consistent.
Ok with those fixed.
Thanks,
Kyrill
> + z0_res = svqshrun_n_u8_s16_x2 (z0, 1),
> + z0_res = svqshrun_u8 (z0, 1))
> +
> +/*
> +** qshrn_z0_z6_8:
> +** sqshrun z0\.b, {z6\.h - z7\.h}, #8
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z6_8, svint16x2_t, svuint8_t,
> + z0_res = svqshrun_n_u8_s16_x2 (z6, 8),
> + z0_res = svqshrun_u8 (z6, 8))
> +
> +/*
> +** qshrn_z0_z29_5:
> +** mov [^\n]+
> +** mov [^\n]+
> +** sqshrun z0\.b, [^\n]+, #5
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z0_z29_5, svint16x2_t, svuint8_t,
> + z0_res = svqshrun_n_u8_s16_x2 (z29, 5),
> + z0_res = svqshrun_u8 (z29, 5))
> +
> +/*
> +** qshrn_z5_z0_3:
> +** sqshrun z5\.b, {z0\.h - z1\.h}, #3
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z5_z0_3, svint16x2_t, svuint8_t,
> + z5 = svqshrun_n_u8_s16_x2 (z0, 3),
> + z5 = svqshrun_u8 (z0, 3))
> +
> +/*
> +** qshrn_z22_z16_7:
> +** sqshrun z22\.b, {z16\.h - z17\.h}, #7
> +** ret
> +*/
> +TEST_X2_NARROW (qshrn_z22_z16_7, svint16x2_t, svuint8_t,
> + z22 = svqshrun_n_u8_s16_x2 (z16, 7),
> + z22 = svqshrun_u8 (z16, 7))
> diff --git a/gcc/testsuite/lib/target-supports.exp
> b/gcc/testsuite/lib/target-supports.exp
> index c6ebbed4f4b..54fb2bbcaaa 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -12887,10 +12887,10 @@ proc
> check_effective_target_aarch64_gas_has_build_attributes { } {
> set exts {
> "bf16" "cmpbr" "crc" "crypto" "dotprod" "f32mm" "f64mm" "faminmax"
> "fp" "fp8" "fp8dot2" "fp8dot4" "fp8fma" "i8mm" "ls64" "lse" "lut"
> - "sb" "simd" "sve-b16b16" "sve" "sve2" "sve-sm4" "sve-aes" "sve-bitperm"
> + "sb" "simd" "sve-b16b16" "sve" "sve2" "sve2p3" "sve-sm4" "sve-aes"
> "sve-bitperm"
> "sve-sha3" "f8f16mm" "f8f32mm" "sve-f16f32mm"
> "sme-f8f16" "sme-f8f32"
> - "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2"
> + "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2"
> "sme2p3"
> "ssve-fp8dot2" "ssve-fp8dot4" "ssve-fp8fma" "sve-bfscale" "sme-lutv2"
> "ssve-fexpa" "ssve-bitperm"
> }
> --
> 2.43.0
>
