Kishan Parmar <[email protected]> issued a patch that made me re-examine the
code I had put out for dense math registers. This patch fixes the third problem
the patch uncovered.
The first problem is the insert/extract instructions were using %<n> to address
VSX registers instead of using %x<n>. This would give the wrong register number
if a vector register 32..63 was used (i.e. a traditional Altivec register).
The second problem was the instructions were using %L<n> to access the second
vector pair register, which does not work for Altivec registers either without
the patch.
I have rewritten the instructions to use %x<n> for the first vector pair
register, and %x<n>+2 to access the second vector pair register.
I have committed all of the patches in my backlog (dense math registers, other
-mcpu=future instructions, random bug fixes, support for _Float16 and
__bfloat16, and optimizations for vector logical operations on power10/power11)
into the IBM vendor branch:
vendors/ibm/gcc-17-future
I have tested these patches on both big endian and little endian PowerPC
servers, with no regressions. Can I check these patches into the trunk?
2026-07-02 Michael Meissner <[email protected]>
gcc/
* config/rs6000/mma.md (movxo_dm): Fix issues if vector registers 32..63
were used.
(movtdo_insert512_upper): Likewise.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
---
gcc/config/rs6000/mma.md | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 16a7bb26e0e..fee6e168a2a 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -383,9 +383,9 @@ (define_insn_and_split "*movxo_dm"
#
#
#
- dmxxinstdmr512 %0,%1,%Y1,0
+ dmxxinstdmr512 %0,%x1,%x1+2,0
dmmr %0,%1
- dmxxextfdmr512 %0,%Y0,%1,0"
+ dmxxextfdmr512 %x0,%x0+2,%1,0"
"&& reload_completed
&& !dmf_register_operand (operands[0], XOmode)
&& !dmf_register_operand (operands[1], XOmode)"
@@ -891,7 +891,7 @@ (define_insn "movtdo_insert512_upper"
(unspec:TDO [(match_operand:XO 1 "vsx_register_operand" "wa")]
UNSPEC_DMF_INSERT512_UPPER))]
"TARGET_DENSE_MATH"
- "dmxxinstdmr512 %0,%1,%Y1,0"
+ "dmxxinstdmr512 %0,%x1,%x1+2,0"
[(set_attr "type" "mma")])
(define_insn "movtdo_insert512_lower"
@@ -900,7 +900,7 @@ (define_insn "movtdo_insert512_lower"
(match_operand:XO 2 "vsx_register_operand" "wa")]
UNSPEC_DMF_INSERT512_LOWER))]
"TARGET_DENSE_MATH"
- "dmxxinstdmr512 %0,%2,%Y2,1"
+ "dmxxinstdmr512 %0,%x2,%x2+2,1"
[(set_attr "type" "mma")])
;; Move from dense math registers to VSX registers via two extract 512 bit
@@ -911,7 +911,7 @@ (define_insn "movtdo_extract512"
(match_operand 2 "const_0_to_1_operand" "n")]
UNSPEC_DMF_EXTRACT512))]
"TARGET_DENSE_MATH"
- "dmxxextfdmr512 %0,%Y0,%1,%2"
+ "dmxxextfdmr512 %x0,%x0+2,%1,%2"
[(set_attr "type" "mma")])
;; Reload dense math registers from memory.
--
2.54.0
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
