From: Pan Li <[email protected]> Implement the new constraint Wov based on Robin's dynamic filter in lra. And apply it to the v[sz]ext.vf2 define insn pattern.
Please *NOTE* it will NOT try to overlap as much as possible. The backend only predicate which reg no pair is valid or not include the overlap and non-overlap. The lra will decide which reg no pair will be picked and it is out of the control of the backend. The below test suites are passed for this patch: 1. The rv64gcv fully regression tests. There should be some env issue of my local tester. Let's wait and see for v2. Pan Li (3): RISC-V: Allow RVV register overlap for v[sz]ext.vf2 RISC-V: Add test cases for vsext.vf2 reg overlap RISC-V: Add test cases for vzext.vf2 reg overlap gcc/config/riscv/constraints.md | 37 ++++- gcc/config/riscv/riscv-protos.h | 6 +- gcc/config/riscv/riscv-v.cc | 51 +++++++ gcc/config/riscv/riscv.cc | 44 +----- gcc/config/riscv/vector.md | 2 +- .../rvv/autovec/group_overlap/group_overlap.h | 131 ++++++++++++++++++ .../autovec/group_overlap/vsext_vf2-i16-m1.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i16-m2.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i16-m4.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i16-mf2.c | 31 +++++ .../autovec/group_overlap/vsext_vf2-i16-mf4.c | 31 +++++ .../autovec/group_overlap/vsext_vf2-i32-m1.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i32-m2.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i32-m4.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i32-mf2.c | 31 +++++ .../autovec/group_overlap/vsext_vf2-i8-m1.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i8-m2.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i8-m4.c | 17 +++ .../autovec/group_overlap/vsext_vf2-i8-mf2.c | 31 +++++ .../autovec/group_overlap/vsext_vf2-i8-mf4.c | 31 +++++ .../autovec/group_overlap/vsext_vf2-i8-mf8.c | 31 +++++ .../autovec/group_overlap/vzext_vf2-u16-m1.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u16-m2.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u16-m4.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u16-mf2.c | 31 +++++ .../autovec/group_overlap/vzext_vf2-u16-mf4.c | 31 +++++ .../autovec/group_overlap/vzext_vf2-u32-m1.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u32-m2.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u32-m4.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u32-mf2.c | 31 +++++ .../autovec/group_overlap/vzext_vf2-u8-m1.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u8-m2.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u8-m4.c | 17 +++ .../autovec/group_overlap/vzext_vf2-u8-mf2.c | 31 +++++ .../autovec/group_overlap/vzext_vf2-u8-mf4.c | 31 +++++ .../autovec/group_overlap/vzext_vf2-u8-mf8.c | 31 +++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 + 37 files changed, 900 insertions(+), 51 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u16-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u16-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u16-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u16-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u16-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u32-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u32-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u32-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u32-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u8-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u8-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u8-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u8-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u8-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf2-u8-mf8.c -- 2.43.0
