On Mon, Jul 13, 2026 at 11:15 PM Uros Bizjak <[email protected]> wrote: > > On Mon, Jul 13, 2026 at 4:26 PM H.J. Lu <[email protected]> wrote: > > > > 1. Add round_zext and round_saeonly_zext to subst.md. > > 2. Use them to add missing SSE and AVX zero-extend patterns. > > 3. Add tests to check for newly added SSE and AVX zero-extend patterns. > > > > gcc/ > > > > PR target/126231 > > * config/i386/i386.md (*fix_trunc<mode>si_sse_zext): New. > > (*fix_trunc<mode>si_sse_2_zext): Likewise. > > * config/i386/sse.md > > (*avx512fp16_vcvtsh2<sseintconvertsignprefix>si<round_zext_name>): > > Likewise. > > (avx512fp16_vcvtsh2<sseintconvertsignprefix>si_2_zext): Likewise. > > (*unspec_avx512fp16_fix<vcvtt_uns_suffix>_truncsi2<round_saeonly_zext_name>): > > Likewise. > > (*sse_cvtss2si<round_zext_name>): Likewise. > > (*sse_cvtss2si_2_zext): Likewise. > > (*unspec_sse_cvttss2si<round_saeonly_zext_name>): Likewise. > > (*sse_cvttss2si<round_saeonly_zext_name>): Likewise. > > (*avx512f_vcvtss2usi<round_zext_name>): Likewise. > > (*unspec_avx512f_vcvttss2usi<round_saeonly_zext_name>): Likewise. > > (*avx512f_vcvttss2usi<round_saeonly_zext_name>): Likewise. > > (*avx512f_vcvtsd2usi<round_zext_name>): Likewise. > > (*unspec_avx512f_vcvttsd2usi<round_saeonly_zext_name>): > > Likewise. > > (*avx512f_vcvttsd2usi<round_saeonly_zext_name>): Likewise. > > (*sse2_cvtsd2si<round_zext_name>): Likewise. > > (*sse2_cvtsd2si_2_zext): Likewise. > > (*unspec_sse2_cvttsd2si<round_saeonly_zext_name>): Likewise. > > (*sse2_cvttsd2si<round_saeonly_zext_name>): Likewise. > > (*avx10_2_vcvttsd2<sat_cvt_sign_prefix>sissi<round_saeonly_zext_name>): > > Likewise. > > (*avx10_2_vcvttss2<sat_cvt_sign_prefix>sissi<round_saeonly_zext_name>): > > Likewise. > > * config/i386/subst.md (round_zext_name): Likewise. > > (round_zext_constraint): Likewise. > > (round_zext_constraint2): Likewise. > > (round_zext_nimm_predicate): Likewise. > > (round_zext_nimm_scalar_predicate): Likewise. > > (round_zext_op2): Likewise. > > (round_zext): Likewise. > > (round_saeonly_zext_name): Likewise. > > (round_saeonly_zext_constraint): Likewise. > > (round_saeonly_zext_constraint2): Likewise. > > (round_saeonly_zext_nimm_scalar_predicate): Likewise. > > (round_saeonly_zext_op2): Likewise. > > (round_saeonly_zext): Likewise. > > > > gcc/testsuite/ > > > > PR target/126231 > > * gcc.target/i386/zext-avx10-1.c: New test. > > * gcc.target/i386/zext-avx512f-1.c: Likewise. > > * gcc.target/i386/zext-avx512fp16-1.c: Likewise. > > * gcc.target/i386/zext-sse-1.c: Likewise. > > * gcc.target/i386/zext-sse-2.c: Likewise. > > +(define_insn "*sse2_cvtsd2si_2_zext" > + [(set (match_operand:DI 0 "register_operand" "=r,r") > + (zero_extend:DI > + (unspec:SWI48 [(match_operand:DF 1 "nonimmediate_operand" "v,m")] > + UNSPEC_FIX_NOTRUNC)))] > + "TARGET_64BIT && TARGET_SSE2" > + "%vcvtsd2si{l}\t{%1, %k0|%k0, %q1}" > > The mode iterator here is wrong. Please put patches through AI review > first, AI immediately flags these kinds of errors, without wasting > reviewers time. >
I am doing it now. Thanks. -- H.J.
