The Dense Math Facility (DMF) is a hardware feature that provides
hardware acceleration for high-throughput, low-precision math operations
used in machine learning inferencing and deep learning workloads. It
also adds acceleration for certain cryptographic algorithms (SHA2, SHA3).
DMF subsumes and extends the functionality of MMA.
Note that DMF may or may not be present in a future Power processor.
Key architectural differences from MMA (ISA 3.1):
- DMF introduces eight dedicated 1024-bit Dense Math Registers (DMRs)
that act as accumulators for outer-product instructions. Unlike MMA
accumulators, DMRs are not overlaid over VSX/FPR registers (VSRs 0..31);
they are a fully separate register file.
- Because DMR accumulators are separate registers, compiling with
-mcpu=future allows GCC to freely allocate up to 32 additional VSX
registers that would otherwise be reserved to back MMA accumulators
under -mcpu=power10 or -mcpu=power11.
- Existing Power10/Power11 MMA instructions operating on 512 bits
remain functional on DMF-capable hardware.
- DMR registers cannot be directly loaded from or stored to memory.
Values must be staged through 8 VSX registers: to store a DMR,
its contents are copied to 8 VSXes which are then stored; to load
a DMR, the value is loaded into 8 VSXes which are then copied into
the DMR.
- Direct support for bfloat16 data elements is provided alongside
IEEE 754 formats to accelerate machine learning applications.
The Vector Scalar Extension (VSX) facility is a prerequisite for DMF.
The patches that add -mdense-math compiler option and a new TDOmode
value have already been upstreamed. There will be a series of patches
submitted to support the Dense Math Facility in Power.
