Hi gcc-patches mailing list, Christopher Bazley via Sourceware Forge <[email protected]> has requested that the following forgejo pull request be published on the mailing list.
Created on: 2026-07-30 16:16:38+00:00 Latest update: 2026-07-30 16:59:53+00:00 Changes: 3 changed files, 12 additions, 12 deletions Head revision: chris.bazley/gcc ref relax-aarch64-tests commit bec1ae564653ab8868fc030ac2f8316a06edc6d4 Base revision: gcc/gcc ref trunk commit ece564fdaa15a0da008cedd881afcd3f0f4dbd5a r17-2824-gece564fdaa15a0 Merge base: ece564fdaa15a0da008cedd881afcd3f0f4dbd5a Full diff url: https://forge.sourceware.org/gcc/gcc/pulls/209.diff Discussion: https://forge.sourceware.org/gcc/gcc/pulls/209 Requested Reviewers: pinskia The -fweb option changes the way that GCC allocates registers. -fweb is not enabled by default, so we have never previously noticed that some AArch64 tests have unreasonably strict expectations about register allocation. This patch relaxes those expectations. gcc/testsuite/ChangeLog: * gcc.target/aarch64/ffs.c: Relax test expectations. * gcc.target/aarch64/frecpe_1.c: As above. * gcc.target/aarch64/frecpe_2.c: As above. Changed files: - M: gcc/testsuite/gcc.target/aarch64/ffs.c - M: gcc/testsuite/gcc.target/aarch64/frecpe_1.c - M: gcc/testsuite/gcc.target/aarch64/frecpe_2.c Christopher Bazley (1): AArch64: Relax regexps in tests to let them pass with -fweb gcc/testsuite/gcc.target/aarch64/ffs.c | 20 ++++++++++---------- gcc/testsuite/gcc.target/aarch64/frecpe_1.c | 2 +- gcc/testsuite/gcc.target/aarch64/frecpe_2.c | 2 +- 3 files changed, 12 insertions(+), 12 deletions(-) Range-diff against v1: 1: 03eaae9336bb ! 1: bec1ae564653 AArch64: Relax regexps in tests to let them pass with -fweb @@ gcc/testsuite/gcc.target/aarch64/ffs.c -** clz w0, w0 -** csinc w0, wzr, w0, eq +** rbit (w[0-9]+), w1 -+** clz \1, \1 -+** csinc w0, wzr, \1, eq ++** clz (w[0-9]+), \1 ++** csinc w0, wzr, \2, eq ** ret */ @@ gcc/testsuite/gcc.target/aarch64/ffs.c: int ffsw1 (int y, uint32_t x) -** clz x0, x0 -** csinc x0, xzr, x0, eq +** rbit (x[0-9]+), x1 -+** clz \1, \1 -+** csinc x0, xzr, \1, eq ++** clz (x[0-9]+), \1 ++** csinc x0, xzr, \2, eq ** ret */ -- 2.54.0
